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Makes AArch64 assembly acceptable to clang
According to ARMv8 architecture reference manual section C7.2.188, SIMD MOV (to general) instruction format is MOV <Xd>, <Vn>.D[<index>] gas appears to accept "<Vn>.2D[<index>]" as well, but clang's assembler does not. C.f. https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/5214/aarch64-assembly-syntax-for-armclang
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@ -91,7 +91,7 @@ ENTRY (__memchr)
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and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
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addp vend.16b, vhas_chr1.16b, vhas_chr2.16b /* 256->128 */
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addp vend.16b, vend.16b, vend.16b /* 128->64 */
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mov synd, vend.2d[0]
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mov synd, vend.d[0]
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/* Clear the soff*2 lower bits */
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lsl tmp, soff, #1
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lsr synd, synd, tmp
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@ -111,7 +111,7 @@ L(loop):
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/* Use a fast check for the termination condition */
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orr vend.16b, vhas_chr1.16b, vhas_chr2.16b
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addp vend.2d, vend.2d, vend.2d
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mov synd, vend.2d[0]
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mov synd, vend.d[0]
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/* We're not out of data, loop if we haven't found the character */
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cbz synd, L(loop)
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@ -121,7 +121,7 @@ L(end):
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and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
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addp vend.16b, vhas_chr1.16b, vhas_chr2.16b /* 256->128 */
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addp vend.16b, vend.16b, vend.16b /* 128->64 */
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mov synd, vend.2d[0]
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mov synd, vend.d[0]
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/* Only do the clear for the last possible block */
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b.hi L(tail)
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@ -94,7 +94,7 @@ ENTRY (strchr)
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addp vend1.16b, vend1.16b, vend2.16b // 128->64
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lsr tmp1, tmp3, tmp1
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mov tmp3, vend1.2d[0]
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mov tmp3, vend1.d[0]
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bic tmp1, tmp3, tmp1 // Mask padding bits.
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cbnz tmp1, L(tail)
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@ -109,7 +109,7 @@ L(loop):
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orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b
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orr vend1.16b, vend1.16b, vend2.16b
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addp vend1.2d, vend1.2d, vend1.2d
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mov tmp1, vend1.2d[0]
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mov tmp1, vend1.d[0]
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cbz tmp1, L(loop)
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/* Termination condition found. Now need to establish exactly why
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@ -123,7 +123,7 @@ L(loop):
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addp vend1.16b, vend1.16b, vend2.16b // 256->128
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addp vend1.16b, vend1.16b, vend2.16b // 128->64
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mov tmp1, vend1.2d[0]
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mov tmp1, vend1.d[0]
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L(tail):
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sub src, src, #32
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rbit tmp1, tmp1
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@ -91,7 +91,7 @@ ENTRY (__strchrnul)
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addp vend1.16b, vend1.16b, vend1.16b // 128->64
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lsr tmp1, tmp3, tmp1
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mov tmp3, vend1.2d[0]
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mov tmp3, vend1.d[0]
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bic tmp1, tmp3, tmp1 // Mask padding bits.
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cbnz tmp1, L(tail)
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@ -106,7 +106,7 @@ L(loop):
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orr vhas_chr2.16b, vhas_nul2.16b, vhas_chr2.16b
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orr vend1.16b, vhas_chr1.16b, vhas_chr2.16b
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addp vend1.2d, vend1.2d, vend1.2d
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mov tmp1, vend1.2d[0]
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mov tmp1, vend1.d[0]
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cbz tmp1, L(loop)
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/* Termination condition found. Now need to establish exactly why
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@ -116,7 +116,7 @@ L(loop):
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addp vend1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
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addp vend1.16b, vend1.16b, vend1.16b // 128->64
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mov tmp1, vend1.2d[0]
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mov tmp1, vend1.d[0]
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L(tail):
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/* Count the trailing zeros, by bit reversing... */
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rbit tmp1, tmp1
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@ -101,10 +101,10 @@ ENTRY(strrchr)
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addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
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addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul1.16b // 128->64
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addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr1.16b // 128->64
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mov nul_match, vhas_nul1.2d[0]
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mov nul_match, vhas_nul1.d[0]
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lsl tmp1, tmp1, #1
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mov const_m1, #~0
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mov chr_match, vhas_chr1.2d[0]
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mov chr_match, vhas_chr1.d[0]
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lsr tmp3, const_m1, tmp1
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bic nul_match, nul_match, tmp3 // Mask padding bits.
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@ -127,15 +127,15 @@ L(aligned):
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addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
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addp vend1.16b, vend1.16b, vend1.16b // 128->64
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addp vhas_chr1.16b, vhas_chr1.16b, vhas_chr1.16b // 128->64
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mov nul_match, vend1.2d[0]
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mov chr_match, vhas_chr1.2d[0]
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mov nul_match, vend1.d[0]
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mov chr_match, vhas_chr1.d[0]
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cbz nul_match, L(loop)
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and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
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and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
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addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul2.16b
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addp vhas_nul1.16b, vhas_nul1.16b, vhas_nul1.16b
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mov nul_match, vhas_nul1.2d[0]
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mov nul_match, vhas_nul1.d[0]
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L(tail):
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/* Work out exactly where the string ends. */
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