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Load cache sizes into R*_LP in memcpy-ssse3.S

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This commit is contained in:
H.J. Lu 2012-05-15 09:58:28 -07:00
parent 6d2850e7f5
commit 9bc0b730a6
2 changed files with 17 additions and 12 deletions
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5
ChangeLog
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@ -1,3 +1,8 @@
2012-05-15 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86_64/multiarch/memcpy-ssse3.S: Load cache sizes
into R*_LP.
2012-05-15 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86_64/multiarch/memcpy-ssse3-back.S: Load cache

24
sysdeps/x86_64/multiarch/memcpy-ssse3.S
View File

@ -97,9 +97,9 @@ L(80bytesormore):
sub %rcx, %rsi
#ifdef SHARED_CACHE_SIZE_HALF
mov $SHARED_CACHE_SIZE_HALF, %rcx
mov $SHARED_CACHE_SIZE_HALF, %RCX_LP
#else
mov __x86_64_shared_cache_size_half(%rip), %rcx
mov __x86_64_shared_cache_size_half(%rip), %RCX_LP
#endif
cmp %rcx, %rdx
mov %rsi, %r9
@ -107,9 +107,9 @@ L(80bytesormore):
and $0xf, %r9
jz L(shl_0)
#ifdef DATA_CACHE_SIZE_HALF
mov $DATA_CACHE_SIZE_HALF, %rcx
mov $DATA_CACHE_SIZE_HALF, %RCX_LP
#else
mov __x86_64_data_cache_size_half(%rip), %rcx
mov __x86_64_data_cache_size_half(%rip), %RCX_LP
#endif
BRANCH_TO_JMPTBL_ENTRY (L(shl_table), %r9, 4)
@ -127,9 +127,9 @@ L(copy_backward):
sub %rcx, %rsi
#ifdef SHARED_CACHE_SIZE_HALF
mov $SHARED_CACHE_SIZE_HALF, %rcx
mov $SHARED_CACHE_SIZE_HALF, %RCX_LP
#else
mov __x86_64_shared_cache_size_half(%rip), %rcx
mov __x86_64_shared_cache_size_half(%rip), %RCX_LP
#endif
cmp %rcx, %rdx
@ -138,9 +138,9 @@ L(copy_backward):
and $0xf, %r9
jz L(shl_0_bwd)
#ifdef DATA_CACHE_SIZE_HALF
mov $DATA_CACHE_SIZE_HALF, %rcx
mov $DATA_CACHE_SIZE_HALF, %RCX_LP
#else
mov __x86_64_data_cache_size_half(%rip), %rcx
mov __x86_64_data_cache_size_half(%rip), %RCX_LP
#endif
BRANCH_TO_JMPTBL_ENTRY (L(shl_table_bwd), %r9, 4)
@ -175,9 +175,9 @@ L(shl_0_less_64bytes):
ALIGN (4)
L(shl_0_gobble):
#ifdef DATA_CACHE_SIZE_HALF
cmp $DATA_CACHE_SIZE_HALF, %rdx
cmp $DATA_CACHE_SIZE_HALF, %RDX_LP
#else
cmp __x86_64_data_cache_size_half(%rip), %rdx
cmp __x86_64_data_cache_size_half(%rip), %RDX_LP
#endif
lea -128(%rdx), %rdx
jae L(shl_0_gobble_mem_loop)
@ -316,9 +316,9 @@ L(shl_0_less_64bytes_bwd):
ALIGN (4)
L(shl_0_gobble_bwd):
#ifdef DATA_CACHE_SIZE_HALF
cmp $DATA_CACHE_SIZE_HALF, %rdx
cmp $DATA_CACHE_SIZE_HALF, %RDX_LP
#else
cmp __x86_64_data_cache_size_half(%rip), %rdx
cmp __x86_64_data_cache_size_half(%rip), %RDX_LP
#endif
lea -128(%rdx), %rdx
jae L(shl_0_gobble_mem_bwd_loop)