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[2/5] AArch64: Improve A64FX memset for large sizes
Improve performance of large memsets. Simplify alignment code. For zero memset use DC ZVA, which almost doubles performance. For non-zero memsets use the unroll8 loop which is about 10% faster. Reviewed-by: Naohiro Tamura <naohirot@fujitsu.com>
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@ -27,14 +27,11 @@
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*/
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#define L1_SIZE (64*1024) // L1 64KB
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#define L2_SIZE (8*1024*1024) // L2 8MB - 1MB
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#define L2_SIZE (8*1024*1024) // L2 8MB
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#define CACHE_LINE_SIZE 256
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#define PF_DIST_L1 (CACHE_LINE_SIZE * 16) // Prefetch distance L1
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#define ZF_DIST (CACHE_LINE_SIZE * 21) // Zerofill distance
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#define rest x8
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#define rest x2
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#define vector_length x9
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#define vl_remainder x10 // vector_length remainder
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#define cl_remainder x11 // CACHE_LINE_SIZE remainder
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#if HAVE_AARCH64_SVE_ASM
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# if IS_IN (libc)
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@ -42,14 +39,6 @@
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.arch armv8.2-a+sve
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.macro dc_zva times
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dc zva, tmp1
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add tmp1, tmp1, CACHE_LINE_SIZE
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.if \times-1
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dc_zva "(\times-1)"
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.endif
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.endm
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.macro st1b_unroll first=0, last=7
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st1b z0.b, p0, [dst, \first, mul vl]
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.if \last-\first
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@ -188,54 +177,30 @@ L(L1_prefetch): // if rest >= L1_SIZE
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cbnz rest, L(unroll32)
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ret
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L(L2):
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// align dst address at vector_length byte boundary
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sub tmp1, vector_length, 1
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ands tmp2, dst, tmp1
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// if vl_remainder == 0
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b.eq 1f
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sub vl_remainder, vector_length, tmp2
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// process remainder until the first vector_length boundary
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whilelt p2.b, xzr, vl_remainder
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st1b z0.b, p2, [dst]
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add dst, dst, vl_remainder
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sub rest, rest, vl_remainder
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// align dstin address at CACHE_LINE_SIZE byte boundary
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1: mov tmp1, CACHE_LINE_SIZE
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ands tmp2, dst, CACHE_LINE_SIZE - 1
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// if cl_remainder == 0
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b.eq L(L2_dc_zva)
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sub cl_remainder, tmp1, tmp2
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// process remainder until the first CACHE_LINE_SIZE boundary
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mov tmp1, xzr // index
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2: whilelt p2.b, tmp1, cl_remainder
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st1b z0.b, p2, [dst, tmp1]
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incb tmp1
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cmp tmp1, cl_remainder
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b.lo 2b
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add dst, dst, cl_remainder
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sub rest, rest, cl_remainder
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L(L2_dc_zva):
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// zero fill
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mov tmp1, dst
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dc_zva (ZF_DIST / CACHE_LINE_SIZE) - 1
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mov zva_len, ZF_DIST
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add tmp1, zva_len, CACHE_LINE_SIZE * 2
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// unroll
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// count >= L2_SIZE
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.p2align 3
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1: st1b_unroll 0, 3
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add tmp2, dst, zva_len
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dc zva, tmp2
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st1b_unroll 4, 7
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add tmp2, tmp2, CACHE_LINE_SIZE
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dc zva, tmp2
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add dst, dst, CACHE_LINE_SIZE * 2
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sub rest, rest, CACHE_LINE_SIZE * 2
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cmp rest, tmp1 // ZF_DIST + CACHE_LINE_SIZE * 2
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b.ge 1b
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cbnz rest, L(unroll8)
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ret
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L(L2):
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tst valw, 255
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b.ne L(unroll8)
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// align dst to CACHE_LINE_SIZE byte boundary
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and tmp2, dst, CACHE_LINE_SIZE - 1
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st1b z0.b, p0, [dst, 0, mul vl]
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st1b z0.b, p0, [dst, 1, mul vl]
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st1b z0.b, p0, [dst, 2, mul vl]
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st1b z0.b, p0, [dst, 3, mul vl]
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sub dst, dst, tmp2
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add count, count, tmp2
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// clear cachelines using DC ZVA
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sub count, count, CACHE_LINE_SIZE * 2
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.p2align 4
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1: add dst, dst, CACHE_LINE_SIZE
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dc zva, dst
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subs count, count, CACHE_LINE_SIZE
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b.hi 1b
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add count, count, CACHE_LINE_SIZE
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add dst, dst, CACHE_LINE_SIZE
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b L(last)
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END (MEMSET)
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libc_hidden_builtin_def (MEMSET)
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