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x86: Set default non_temporal_threshold for Zhaoxin processors
Current 'non_temporal_threshold' set to 'non_temporal_threshold_lowbound' on Zhaoxin processors without ERMS. The default 'non_temporal_threshold_lowbound' is too small for the KH-40000 and KX-7000 Zhaoxin processors, this patch updates the value to 'shared / cachesize_non_temporal_divisor'. Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
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@ -1065,6 +1065,7 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht
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/* Yongfeng and Shijidadao mircoarch tuning. */
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case 0x5b:
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cpu_features->cachesize_non_temporal_divisor = 2;
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case 0x6b:
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cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
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&= ~bit_arch_AVX_Fast_Unaligned_Load;
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@ -934,8 +934,10 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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/* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
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a higher risk of actually thrashing the cache as they don't have a HW LRU
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hint. As well, their performance in highly parallel situations is
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noticeably worse. */
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if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
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noticeably worse. Zhaoxin processors are an exception, the lowbound is not
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suitable for them based on actual test data. */
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if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)
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&& cpu_features->basic.kind != arch_kind_zhaoxin)
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non_temporal_threshold = non_temporal_threshold_lowbound;
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/* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
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'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
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