AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-11-21 12:30:06 +00:00
Code Issues Packages Projects Releases Wiki Activity

x86: Set default non_temporal_threshold for Zhaoxin processors

Browse Source 
Current 'non_temporal_threshold' set to 'non_temporal_threshold_lowbound'
on Zhaoxin processors without ERMS. The default
'non_temporal_threshold_lowbound' is too small for the KH-40000 and KX-7000
Zhaoxin processors, this patch updates the value to
'shared / cachesize_non_temporal_divisor'.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
This commit is contained in:
MayShao-oc 2024-06-29 11:58:28 +08:00 committed by H.J. Lu
parent c19457aec6
commit 9dc645cb56
2 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
sysdeps/x86/cpu-features.c
View File

@ -1065,6 +1065,7 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht
/* Yongfeng and Shijidadao mircoarch tuning. */
case 0x5b:
cpu_features->cachesize_non_temporal_divisor = 2;
case 0x6b:
cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
&= ~bit_arch_AVX_Fast_Unaligned_Load;

6
sysdeps/x86/dl-cacheinfo.h
View File

@ -934,8 +934,10 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
/* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
a higher risk of actually thrashing the cache as they don't have a HW LRU
hint. As well, their performance in highly parallel situations is
noticeably worse. */
if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
noticeably worse. Zhaoxin processors are an exception, the lowbound is not
suitable for them based on actual test data. */
if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)
&& cpu_features->basic.kind != arch_kind_zhaoxin)
non_temporal_threshold = non_temporal_threshold_lowbound;
/* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best