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ARM: Support avoiding pc as destination register.
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@ -1,3 +1,10 @@
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2013-03-13 Roland McGrath <roland@hack.frob.com>
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* sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
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* sysdeps/arm/memcpy.S: Include <arm-features.h>.
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[ARM_ALWAYS_BX]: Avoid pc as destination.
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* sysdeps/arm/memmove.S: Likewise.
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2013-03-12 Roland McGrath <roland@hack.frob.com>
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* sysdeps/arm/armv6t2/memchr.S [NO_THUMB]:
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@ -36,4 +36,8 @@
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at runtime (or that we never care about its state) and so need not
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be checked for. */
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/* A more-specific arm-features.h file may define ARM_ALWAYS_BX to indicate
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that instructions using pc as a destination register must never be used,
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so a "bx" (or "blx") instruction is always required. */
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#endif /* arm-features.h */
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@ -20,6 +20,7 @@
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/* Thumb requires excessive IT insns here. */
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#define NO_THUMB
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#include <sysdep.h>
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#include <arm-features.h>
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/*
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* Data preload for architectures that support it (ARM V5TE and above)
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@ -89,7 +90,12 @@ ENTRY(memcpy)
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, r3 ) @ C gets set
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#ifndef ARM_ALWAYS_BX
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CALGN( add pc, r4, ip )
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#else
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CALGN( add r4, r4, ip )
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CALGN( bx r4 )
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#endif
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PLD( pld [r1, #0] )
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2: PLD( subs r2, r2, #96 )
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@ -108,8 +114,17 @@ ENTRY(memcpy)
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5: ands ip, r2, #28
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rsb ip, ip, #32
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#ifndef ARM_ALWAYS_BX
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addne pc, pc, ip @ C is always clear here
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b 7f
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#else
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beq 7f
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push {r10}
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cfi_adjust_cfa_offset (4)
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cfi_rel_offset (r10, 0)
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add r10, pc, ip
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bx r10
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#endif
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6: nop
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ldr r3, [r1], #4
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ldr r4, [r1], #4
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@ -119,8 +134,13 @@ ENTRY(memcpy)
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ldr r8, [r1], #4
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ldr lr, [r1], #4
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#ifndef ARM_ALWAYS_BX
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add pc, pc, ip
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nop
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#else
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add r10, pc, ip
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bx r10
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#endif
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nop
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str r3, [r0], #4
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str r4, [r0], #4
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@ -130,6 +150,12 @@ ENTRY(memcpy)
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str r8, [r0], #4
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str lr, [r0], #4
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#ifdef ARM_ALWAYS_BX
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pop {r10}
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cfi_adjust_cfa_offset (-4)
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cfi_restore (r10)
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#endif
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CALGN( bcs 2b )
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7: pop {r5 - r8}
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@ -147,7 +173,8 @@ ENTRY(memcpy)
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strbcs r4, [r0], #1
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strbcs ip, [r0]
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#if defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)
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#if ((defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)) \
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|| defined (ARM_ALWAYS_BX))
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pop {r0, r4, lr}
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cfi_adjust_cfa_offset (-12)
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cfi_restore (r4)
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@ -20,6 +20,7 @@
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/* Thumb requires excessive IT insns here. */
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#define NO_THUMB
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#include <sysdep.h>
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#include <arm-features.h>
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/*
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* Data preload for architectures that support it (ARM V5TE and above)
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@ -105,7 +106,12 @@ ENTRY(memmove)
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, ip ) @ C is set here
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#ifndef ARM_ALWAYS_BX
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CALGN( add pc, r4, ip )
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#else
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CALGN( add r4, r4, ip )
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CALGN( bx r4 )
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#endif
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PLD( pld [r1, #-4] )
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2: PLD( subs r2, r2, #96 )
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@ -124,8 +130,17 @@ ENTRY(memmove)
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5: ands ip, r2, #28
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rsb ip, ip, #32
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#ifndef ARM_ALWAYS_BX
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addne pc, pc, ip @ C is always clear here
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b 7f
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#else
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beq 7f
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push {r10}
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cfi_adjust_cfa_offset (4)
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cfi_rel_offset (r10, 0)
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add r10, pc, ip
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bx r10
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#endif
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6: nop
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ldr r3, [r1, #-4]!
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ldr r4, [r1, #-4]!
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@ -135,8 +150,13 @@ ENTRY(memmove)
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ldr r8, [r1, #-4]!
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ldr lr, [r1, #-4]!
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#ifndef ARM_ALWAYS_BX
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add pc, pc, ip
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nop
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#else
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add r10, pc, ip
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bx r10
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#endif
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nop
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str r3, [r0, #-4]!
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str r4, [r0, #-4]!
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@ -146,6 +166,12 @@ ENTRY(memmove)
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str r8, [r0, #-4]!
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str lr, [r0, #-4]!
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#ifdef ARM_ALWAYS_BX
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pop {r10}
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cfi_adjust_cfa_offset (-4)
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cfi_restore (r10)
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#endif
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CALGN( bcs 2b )
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7: pop {r5 - r8}
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@ -163,7 +189,8 @@ ENTRY(memmove)
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strbcs r4, [r0, #-1]!
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strbcs ip, [r0, #-1]
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#if defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)
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#if ((defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)) \
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|| defined (ARM_ALWAYS_BX))
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pop {r0, r4, lr}
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cfi_adjust_cfa_offset (-12)
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cfi_restore (r4)
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