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Save/restore bound registers in _dl_runtime_resolve
This patch saves and restores bound registers in symbol lookup for x86-64: 1. Branches without BND prefix clear bound registers. 2. x86-64 pass bounds in bound registers as specified in MPX psABI extension on hjl/mpx/master branch at https://github.com/hjl-tools/x86-64-psABI https://groups.google.com/forum/#!topic/x86-64-abi/KFsB0XTgWYc Binutils has been updated to create an alternate PLT to add BND prefix when branching to ld.so. * config.h.in (HAVE_MPX_SUPPORT): New #undef. * sysdeps/x86_64/configure.ac: Set HAVE_MPX_SUPPORT. * sysdeps/x86_64/configure: Regenerated. * sysdeps/x86_64/dl-trampoline.S (REGISTER_SAVE_AREA): New macro. (REGISTER_SAVE_RAX): Likewise. (REGISTER_SAVE_RCX): Likewise. (REGISTER_SAVE_RDX): Likewise. (REGISTER_SAVE_RSI): Likewise. (REGISTER_SAVE_RDI): Likewise. (REGISTER_SAVE_R8): Likewise. (REGISTER_SAVE_R9): Likewise. (REGISTER_SAVE_BND0): Likewise. (REGISTER_SAVE_BND1): Likewise. (REGISTER_SAVE_BND2): Likewise. (_dl_runtime_resolve): Use them. Save and restore Intel MPX bound registers when calling _dl_fixup.
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ChangeLog
21
ChangeLog
@ -1,3 +1,24 @@
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2014-04-09 Igor Zamyatin <igor.zamyatin@intel.com>
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H.J. Lu <hongjiu.lu@intel.com>
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* config.h.in (HAVE_MPX_SUPPORT): New #undef.
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* sysdeps/x86_64/configure.ac: Set HAVE_MPX_SUPPORT.
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* sysdeps/x86_64/configure: Regenerated.
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* sysdeps/x86_64/dl-trampoline.S (REGISTER_SAVE_AREA): New
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macro.
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(REGISTER_SAVE_RAX): Likewise.
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(REGISTER_SAVE_RCX): Likewise.
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(REGISTER_SAVE_RDX): Likewise.
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(REGISTER_SAVE_RSI): Likewise.
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(REGISTER_SAVE_RDI): Likewise.
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(REGISTER_SAVE_R8): Likewise.
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(REGISTER_SAVE_R9): Likewise.
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(REGISTER_SAVE_BND0): Likewise.
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(REGISTER_SAVE_BND1): Likewise.
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(REGISTER_SAVE_BND2): Likewise.
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(_dl_runtime_resolve): Use them. Save and restore Intel MPX
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bound registers when calling _dl_fixup.
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2014-04-09 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
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* bits/string.h (_STRING_ARCH_unaligned): Define it to 0.
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@ -104,6 +104,9 @@
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/* Define if assembler supports AVX512. */
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#undef HAVE_AVX512_ASM_SUPPORT
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/* Define if assembler supports Intel MPX. */
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#undef HAVE_MPX_SUPPORT
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/* Define if gcc supports FMA4. */
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#undef HAVE_FMA4_SUPPORT
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27
sysdeps/x86_64/configure
vendored
27
sysdeps/x86_64/configure
vendored
@ -222,6 +222,33 @@ $as_echo "$libc_cv_cc_novzeroupper" >&6; }
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config_vars="$config_vars
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config-cflags-novzeroupper = $libc_cv_cc_novzeroupper"
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for Intel MPX support" >&5
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$as_echo_n "checking for Intel MPX support... " >&6; }
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if ${libc_cv_asm_mpx+:} false; then :
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$as_echo_n "(cached) " >&6
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else
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cat > conftest.s <<\EOF
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bndmov %bnd0,(%rsp)
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EOF
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if { ac_try='${CC-cc} -c $ASFLAGS conftest.s 1>&5'
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{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
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(eval $ac_try) 2>&5
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ac_status=$?
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$as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
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test $ac_status = 0; }; }; then
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libc_cv_asm_mpx=yes
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else
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libc_cv_asm_mpx=no
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fi
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rm -f conftest*
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fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_mpx" >&5
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$as_echo "$libc_cv_asm_mpx" >&6; }
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if test $libc_cv_asm_mpx == yes; then
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$as_echo "#define HAVE_MPX_SUPPORT 1" >>confdefs.h
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fi
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$as_echo "#define PI_STATIC_AND_HIDDEN 1" >>confdefs.h
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# work around problem with autoconf and empty lines at the end of files
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@ -75,6 +75,21 @@ LIBC_TRY_CC_OPTION([-mno-vzeroupper],
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])
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LIBC_CONFIG_VAR([config-cflags-novzeroupper], [$libc_cv_cc_novzeroupper])
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dnl Check whether asm supports Intel MPX
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AC_CACHE_CHECK(for Intel MPX support, libc_cv_asm_mpx, [dnl
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cat > conftest.s <<\EOF
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bndmov %bnd0,(%rsp)
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EOF
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if AC_TRY_COMMAND(${CC-cc} -c $ASFLAGS conftest.s 1>&AS_MESSAGE_LOG_FD); then
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libc_cv_asm_mpx=yes
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else
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libc_cv_asm_mpx=no
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fi
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rm -f conftest*])
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if test $libc_cv_asm_mpx == yes; then
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AC_DEFINE(HAVE_MPX_SUPPORT)
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fi
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dnl It is always possible to access static and hidden symbols in an
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dnl position independent way.
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AC_DEFINE(PI_STATIC_AND_HIDDEN)
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@ -24,6 +24,30 @@
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# error RTLD_SAVESPACE_SSE must be aligned to 32 bytes
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#endif
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/* Area on stack to save and restore registers used for parameter
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passing when calling _dl_fixup. */
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#ifdef __ILP32__
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/* X32 saves RCX, RDX, RSI, RDI, R8 and R9 plus RAX. */
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# define REGISTER_SAVE_AREA (8 * 7)
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# define REGISTER_SAVE_RAX 0
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#else
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/* X86-64 saves RCX, RDX, RSI, RDI, R8 and R9 plus RAX as well as BND0,
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BND1, BND2, BND3. */
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# define REGISTER_SAVE_AREA (8 * 7 + 16 * 4)
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/* Align bound register save area to 16 bytes. */
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# define REGISTER_SAVE_BND0 0
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# define REGISTER_SAVE_BND1 (REGISTER_SAVE_BND0 + 16)
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# define REGISTER_SAVE_BND2 (REGISTER_SAVE_BND1 + 16)
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# define REGISTER_SAVE_BND3 (REGISTER_SAVE_BND2 + 16)
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# define REGISTER_SAVE_RAX (REGISTER_SAVE_BND3 + 16)
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#endif
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#define REGISTER_SAVE_RCX (REGISTER_SAVE_RAX + 8)
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#define REGISTER_SAVE_RDX (REGISTER_SAVE_RCX + 8)
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#define REGISTER_SAVE_RSI (REGISTER_SAVE_RDX + 8)
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#define REGISTER_SAVE_RDI (REGISTER_SAVE_RSI + 8)
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#define REGISTER_SAVE_R8 (REGISTER_SAVE_RDI + 8)
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#define REGISTER_SAVE_R9 (REGISTER_SAVE_R8 + 8)
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.text
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.globl _dl_runtime_resolve
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.type _dl_runtime_resolve, @function
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@ -31,28 +55,63 @@
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cfi_startproc
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_dl_runtime_resolve:
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cfi_adjust_cfa_offset(16) # Incorporate PLT
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subq $56,%rsp
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cfi_adjust_cfa_offset(56)
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movq %rax,(%rsp) # Preserve registers otherwise clobbered.
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movq %rcx, 8(%rsp)
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movq %rdx, 16(%rsp)
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movq %rsi, 24(%rsp)
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movq %rdi, 32(%rsp)
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movq %r8, 40(%rsp)
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movq %r9, 48(%rsp)
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movq 64(%rsp), %rsi # Copy args pushed by PLT in register.
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movq 56(%rsp), %rdi # %rdi: link_map, %rsi: reloc_index
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subq $REGISTER_SAVE_AREA,%rsp
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cfi_adjust_cfa_offset(REGISTER_SAVE_AREA)
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# Preserve registers otherwise clobbered.
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movq %rax, REGISTER_SAVE_RAX(%rsp)
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movq %rcx, REGISTER_SAVE_RCX(%rsp)
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movq %rdx, REGISTER_SAVE_RDX(%rsp)
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movq %rsi, REGISTER_SAVE_RSI(%rsp)
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movq %rdi, REGISTER_SAVE_RDI(%rsp)
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movq %r8, REGISTER_SAVE_R8(%rsp)
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movq %r9, REGISTER_SAVE_R9(%rsp)
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#ifndef __ILP32__
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# We also have to preserve bound registers. These are nops if
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# Intel MPX isn't available or disabled.
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# ifdef HAVE_MPX_SUPPORT
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bndmov %bnd0, REGISTER_SAVE_BND0(%rsp)
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bndmov %bnd1, REGISTER_SAVE_BND1(%rsp)
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bndmov %bnd2, REGISTER_SAVE_BND2(%rsp)
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bndmov %bnd3, REGISTER_SAVE_BND3(%rsp)
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# else
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.byte 0x66,0x0f,0x1b,0x44,0x24,REGISTER_SAVE_BND0
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.byte 0x66,0x0f,0x1b,0x4c,0x24,REGISTER_SAVE_BND1
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.byte 0x66,0x0f,0x1b,0x54,0x24,REGISTER_SAVE_BND2
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.byte 0x66,0x0f,0x1b,0x5c,0x24,REGISTER_SAVE_BND3
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# endif
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#endif
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# Copy args pushed by PLT in register.
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# %rdi: link_map, %rsi: reloc_index
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movq (REGISTER_SAVE_AREA + 8)(%rsp), %rsi
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movq REGISTER_SAVE_AREA(%rsp), %rdi
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call _dl_fixup # Call resolver.
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movq %rax, %r11 # Save return value
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movq 48(%rsp), %r9 # Get register content back.
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movq 40(%rsp), %r8
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movq 32(%rsp), %rdi
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movq 24(%rsp), %rsi
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movq 16(%rsp), %rdx
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movq 8(%rsp), %rcx
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movq (%rsp), %rax
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addq $72, %rsp # Adjust stack(PLT did 2 pushes)
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cfi_adjust_cfa_offset(-72)
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#ifndef __ILP32__
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# Restore bound registers. These are nops if Intel MPX isn't
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# avaiable or disabled.
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# ifdef HAVE_MPX_SUPPORT
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bndmov REGISTER_SAVE_BND3(%rsp), %bnd3
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bndmov REGISTER_SAVE_BND2(%rsp), %bnd2
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bndmov REGISTER_SAVE_BND1(%rsp), %bnd1
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bndmov REGISTER_SAVE_BND0(%rsp), %bnd0
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# else
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.byte 0x66,0x0f,0x1a,0x5c,0x24,REGISTER_SAVE_BND3
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.byte 0x66,0x0f,0x1a,0x54,0x24,REGISTER_SAVE_BND2
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.byte 0x66,0x0f,0x1a,0x4c,0x24,REGISTER_SAVE_BND1
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.byte 0x66,0x0f,0x1a,0x44,0x24,REGISTER_SAVE_BND0
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# endif
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#endif
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# Get register content back.
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movq REGISTER_SAVE_R9(%rsp), %r9
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movq REGISTER_SAVE_R8(%rsp), %r8
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movq REGISTER_SAVE_RDI(%rsp), %rdi
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movq REGISTER_SAVE_RSI(%rsp), %rsi
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movq REGISTER_SAVE_RDX(%rsp), %rdx
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movq REGISTER_SAVE_RCX(%rsp), %rcx
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movq REGISTER_SAVE_RAX(%rsp), %rax
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# Adjust stack(PLT did 2 pushes)
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addq $(REGISTER_SAVE_AREA + 16), %rsp
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cfi_adjust_cfa_offset(-(REGISTER_SAVE_AREA + 16))
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jmp *%r11 # Jump to function address.
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cfi_endproc
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.size _dl_runtime_resolve, .-_dl_runtime_resolve
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