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https://sourceware.org/git/glibc.git
synced 2024-12-02 09:40:13 +00:00
(platform): Add missing Ruffian entry.
This commit is contained in:
Ulrich Drepper
parent
641d707400
commit
a8d236a8b7
@ -66,14 +66,72 @@
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#define CIA_SPARSE_MEM (0xfffffc8000000000UL)
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#define CIA_DENSE_MEM (0xfffffc8600000000UL)
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/* SABLE is EV4, GAMMA is EV5 */
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#define T2_IO_BASE (0xfffffc03a0000000UL)
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#define T2_SPARSE_MEM (0xfffffc0200000000UL)
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#define T2_DENSE_MEM (0xfffffc03c0000000UL)
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#define GAMMA_IO_BASE (0xfffffc83a0000000UL)
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#define GAMMA_SPARSE_MEM (0xfffffc8200000000UL)
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#define GAMMA_DENSE_MEM (0xfffffc83c0000000UL)
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/* these are for the RAWHIDE family */
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#define MCPCIA_IO_BASE (0xfffffcf980000000UL)
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#define MCPCIA_SPARSE_MEM (0xfffffcf800000000UL)
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#define MCPCIA_DENSE_MEM (0xfffffcf900000000UL)
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/* Tsunami has no SPARSE space */
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/* NOTE: these are hardwired to PCI bus 0 addresses!!! */
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/* Also, these are PHYSICAL, as/so there's no KSEG translation */
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#define TSUNAMI_IO_BASE (0x00000801fc000000UL + 0xfffffc0000000000UL)
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#define TSUNAMI_DENSE_MEM (0x0000080000000000UL + 0xfffffc0000000000UL)
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typedef enum {
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IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_T2
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IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_T2,
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IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_CPUDEP
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} iosys_t;
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static struct io_system {
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int hae_shift;
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unsigned long int bus_memory_base;
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unsigned long int sparse_bus_mem_base;
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unsigned long int bus_io_base;
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} io_system[] = { /* NOTE! must match iosys_t enumeration */
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/* UNKNOWN */ {0, 0, 0, 0},
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/* JENSEN */ {7, 0, JENSEN_SPARSE_MEM, JENSEN_IO_BASE},
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/* APECS */ {5, APECS_DENSE_MEM, APECS_SPARSE_MEM, APECS_IO_BASE},
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/* CIA */ {5, CIA_DENSE_MEM, CIA_SPARSE_MEM, CIA_IO_BASE},
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/* T2 */ {5, T2_DENSE_MEM, T2_SPARSE_MEM, T2_IO_BASE},
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/* TSUNAMI */ {0, TSUNAMI_DENSE_MEM, 0, TSUNAMI_IO_BASE},
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/* MCPCIA */ {5, MCPCIA_DENSE_MEM, MCPCIA_SPARSE_MEM, MCPCIA_IO_BASE},
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/* GAMMA */ {5, GAMMA_DENSE_MEM, GAMMA_SPARSE_MEM, GAMMA_IO_BASE},
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/* CPUDEP */ {0, 0, 0, 0},
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};
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static struct platform {
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const char *name;
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iosys_t io_sys;
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} platform[] = {
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{"Alcor", IOSYS_CIA},
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{"Avanti", IOSYS_APECS},
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{"XL", IOSYS_APECS},
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{"Cabriolet", IOSYS_APECS},
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{"EB164", IOSYS_CIA},
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{"EB64+", IOSYS_APECS},
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{"EB66", IOSYS_APECS},
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{"EB66P", IOSYS_APECS},
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{"Jensen", IOSYS_JENSEN},
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{"Mikasa", IOSYS_CPUDEP},
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{"Noritake", IOSYS_CPUDEP},
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{"Noname", IOSYS_APECS},
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{"Sable", IOSYS_CPUDEP},
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{"Miata", IOSYS_CIA},
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{"Tsunami", IOSYS_TSUNAMI},
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{"Rawhide", IOSYS_MCPCIA},
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{"Ruffian", IOSYS_CIA},
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{"Takara", IOSYS_CIA},
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};
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struct ioswtch {
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void (*sethae)(unsigned long int addr);
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void (*outb)(unsigned char b, unsigned long int port);
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@ -84,30 +142,6 @@ struct ioswtch {
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unsigned int (*inl)(unsigned long int port);
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};
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static struct platform {
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const char *name;
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int io_sys;
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iosys_t hae_shift;
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unsigned long int bus_memory_base;
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unsigned long int sparse_bus_memory_base;
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} platform[] = {
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{"Alcor", IOSYS_CIA, 5, CIA_DENSE_MEM, CIA_SPARSE_MEM},
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{"Avanti", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"Cabriolet", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"EB164", IOSYS_CIA, 5, CIA_DENSE_MEM, CIA_SPARSE_MEM},
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{"EB64+", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"EB66", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"EB66P", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"Jensen", IOSYS_JENSEN, 7, 0, JENSEN_SPARSE_MEM},
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{"Mikasa", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"Mustang", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"Noname", IOSYS_APECS, 5, APECS_DENSE_MEM, APECS_SPARSE_MEM},
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{"Sable", IOSYS_T2, 5, T2_DENSE_MEM, T2_SPARSE_MEM},
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{"Miata", IOSYS_CIA, 5, CIA_DENSE_MEM, CIA_SPARSE_MEM},
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{"Ruffian", IOSYS_CIA, 5, CIA_DENSE_MEM, CIA_SPARSE_MEM},
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};
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static struct {
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struct hae {
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unsigned long int cache;
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@ -130,6 +164,8 @@ port_to_cpu_addr (unsigned long int port, iosys_t iosys, int size)
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{
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if (iosys == IOSYS_JENSEN)
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return (port << 7) + ((size - 1) << 5) + io.base;
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else if (iosys == IOSYS_TSUNAMI)
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return port + io.base;
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else
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return (port << 5) + ((size - 1) << 3) + io.base;
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}
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@ -194,9 +230,6 @@ inline_outl (unsigned int b, unsigned long int port, iosys_t iosys)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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if (port >= MAX_PORT)
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return;
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inline_sethae (0, iosys);
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*(vuip)addr = b;
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mb ();
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@ -236,6 +269,75 @@ inline_inl (unsigned long int port, iosys_t iosys)
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return *(vuip) addr;
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}
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/*
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* Now define the inline functions for CPUs supporting byte/word insns,
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* and whose core logic supports I/O space accesses utilizing them.
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*
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* These routines could be used by MIATA, for example, because it has
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* and EV56 plus PYXIS, but it currently uses SPARSE anyway.
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*
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* These routines are necessary for TSUNAMI/TYPHOON based platforms,
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* which will have (at least) EV6.
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*/
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static inline void
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inline_bwx_outb (unsigned char b, unsigned long int port, iosys_t iosys)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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__asm__ __volatile__ ("stb %1,%0" : : "m"(*(unsigned char *)addr), "r"(b));
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mb ();
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}
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static inline void
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inline_bwx_outw (unsigned short int b, unsigned long int port, iosys_t iosys)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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__asm__ __volatile__ ("stw %1,%0" : : "m"(*(unsigned short *)addr), "r"(b));
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mb ();
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}
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static inline void
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inline_bwx_outl (unsigned int b, unsigned long int port, iosys_t iosys)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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*(vuip)addr = b;
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mb ();
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}
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static inline unsigned int
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inline_bwx_inb (unsigned long int port, iosys_t iosys)
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{
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unsigned long int r, addr = port_to_cpu_addr (port, iosys, 1);
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__asm__ __volatile__ ("ldbu %0,%1" : "=r"(r) : "m"(*(unsigned char *)addr));
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return 0xffUL & r;
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}
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static inline unsigned int
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inline_bwx_inw (unsigned long int port, iosys_t iosys)
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{
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unsigned long int r, addr = port_to_cpu_addr (port, iosys, 1);
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__asm__ __volatile__ ("ldwu %0,%1" : "=r"(r) : "m"(*(unsigned short *)addr));
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return 0xffffUL & r;
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}
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static inline unsigned int
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inline_bwx_inl (unsigned long int port, iosys_t iosys)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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return *(vuip) addr;
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}
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#define DCL_SETHAE(name, iosys) \
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static void \
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@ -259,6 +361,28 @@ name##_##func (unsigned long int addr) \
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return inline_##func (addr, IOSYS_##iosys); \
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}
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#define DCL_SETHAE_IGNORE(name, iosys) \
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static void \
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name##_sethae (unsigned long int addr) \
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{ \
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/* do nothing */ \
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}
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#define DCL_OUT_BWX(name, func, type, iosys) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_bwx_##func (b, addr, IOSYS_##iosys); \
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}
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#define DCL_IN_BWX(name, func, iosys) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_bwx_##func (addr, IOSYS_##iosys); \
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}
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DCL_SETHAE(jensen, JENSEN)
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DCL_OUT(jensen, outb, char, JENSEN)
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@ -279,7 +403,15 @@ DCL_IN(apecs, inb, APECS)
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DCL_IN(apecs, inw, APECS)
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DCL_IN(apecs, inl, APECS)
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struct ioswtch ioswtch[] = {
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DCL_SETHAE_IGNORE(tsunami, TSUNAMI)
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DCL_OUT_BWX(tsunami, outb, char, TSUNAMI)
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DCL_OUT_BWX(tsunami, outw, short int, TSUNAMI)
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DCL_OUT_BWX(tsunami, outl, int, TSUNAMI)
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DCL_IN_BWX(tsunami, inb, TSUNAMI)
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DCL_IN_BWX(tsunami, inw, TSUNAMI)
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DCL_IN_BWX(tsunami, inl, TSUNAMI)
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static struct ioswtch ioswtch[] = {
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{
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jensen_sethae,
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jensen_outb, jensen_outw, jensen_outl,
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@ -289,6 +421,11 @@ struct ioswtch ioswtch[] = {
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apecs_sethae,
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apecs_outb, apecs_outw, apecs_outl,
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apecs_inb, apecs_inw, apecs_inl
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},
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{
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tsunami_sethae,
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tsunami_outb, tsunami_outw, tsunami_outl,
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tsunami_inb, tsunami_inw, tsunami_inl
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}
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};
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@ -358,12 +495,54 @@ init_iosys (void)
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{
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if (strcmp (platform[i].name, systype) == 0)
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{
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io.hae_shift = platform[i].hae_shift;
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io.bus_memory_base = platform[i].bus_memory_base;
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io.sparse_bus_memory_base = platform[i].sparse_bus_memory_base;
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io.sys = platform[i].io_sys;
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/* some platforms can have either EV4 or EV5 CPUs */
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if (io.sys == IOSYS_CPUDEP)
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{
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FILE * fp;
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char cputype[256];
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fp = fopen (PATH_CPUINFO, "r");
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if (fp == NULL)
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return -1;
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while ((n = fscanf (fp, "cpu model : %256[^\n]\n", cputype))
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!= EOF
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&& n != 1)
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fgets (cputype, 256, fp);
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fclose (fp);
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if (strcmp (platform[i].name, "Sable") == 0)
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{
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if (strncmp (cputype, "EV4", 3) == 0)
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io.sys = IOSYS_T2;
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else if (strncmp (cputype, "EV5", 3) == 0)
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io.sys = IOSYS_GAMMA;
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}
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else
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{
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if (strncmp (cputype, "EV4", 3) == 0)
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io.sys = IOSYS_APECS;
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else if (strncmp (cputype, "EV5", 3) == 0)
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io.sys = IOSYS_CIA;
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}
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if (n == EOF || io.sys == IOSYS_CPUDEP)
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{
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/* This can happen if the format of /proc/cpuinfo changes.*/
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fprintf (stderr, "ioperm.init_iosys(): Unable to determine"
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" CPU model.\n");
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__set_errno (ENODEV);
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return -1;
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}
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}
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io.hae_shift = io_system[io.sys].hae_shift;
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io.bus_memory_base = io_system[io.sys].bus_memory_base;
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io.sparse_bus_memory_base = io_system[io.sys].sparse_bus_mem_base;
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io.io_base = io_system[io.sys].bus_io_base;
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if (io.sys == IOSYS_JENSEN)
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io.swp = &ioswtch[0];
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else if (io.sys == IOSYS_TSUNAMI)
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io.swp = &ioswtch[2];
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else
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io.swp = &ioswtch[1];
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return 0;
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@ -396,32 +575,22 @@ _ioperm (unsigned long int from, unsigned long int num, int turn_on)
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{
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if (!io.base)
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{
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unsigned long int base;
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int fd;
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io.hae.reg = 0; /* not used in user-level */
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io.hae.cache = 0;
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if (io.sys != IOSYS_TSUNAMI)
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__sethae (io.hae.cache); /* synchronize with hw */
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fd = open ("/dev/mem", O_RDWR);
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if (fd < 0)
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return fd;
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switch (io.sys)
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{
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case IOSYS_UNKNOWN: base = io.io_base; break;
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case IOSYS_JENSEN: base = JENSEN_IO_BASE; break;
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case IOSYS_APECS: base = APECS_IO_BASE; break;
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case IOSYS_CIA: base = CIA_IO_BASE; break;
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default:
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__set_errno (ENODEV);
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return -1;
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}
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addr = port_to_cpu_addr (0, io.sys, 1);
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len = port_to_cpu_addr (MAX_PORT, io.sys, 1) - addr;
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io.base =
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(unsigned long int) __mmap (0, len, PROT_NONE, MAP_SHARED,
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fd, base);
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fd, io.io_base);
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close (fd);
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if ((long) io.base == -1)
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return -1;
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