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* sysdeps/powerpc/elf/libc-start.c
(__cache_line_size): Declare. (__aux_init_cache): New. (__libc_start_main): Change type of `auxvec' parameter to `ElfW(auxv_t) *'. Correct walking of aux vector. Call __aux_init_cache. * sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c (__cache_line_size): Declare. (__aux_init_cache): New. (DL_PLATFORM_INIT): Define. * sysdeps/powerpc/memset.S: Define __cache_line_size and use its value to select the correct stride for dcbz.
This commit is contained in:
Andreas Jaeger
parent
4343130e1d
commit
adb89120bb
@ -1,4 +1,4 @@
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/* Copyright (C) 1998, 2000, 2001 Free Software Foundation, Inc.
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/* Copyright (C) 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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@ -26,6 +26,10 @@ extern void __libc_init_first (int argc, char **argv, char **envp);
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extern int _dl_starting_up;
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weak_extern (_dl_starting_up)
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extern int __cache_line_size;
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weak_extern (__cache_line_size)
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extern int __libc_multiple_libcs;
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extern void *__libc_stack_end;
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@ -37,12 +41,33 @@ struct startup_info
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void (*fini) (void);
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};
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/* Scan the Aux Vector for the "Data Cache Block Size" entry. If found
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verify that the static extern __cache_line_size is defined by checking
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for not NULL. If it is defined then assign the cache block size
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value to __cache_line_size. */
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static inline void
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__aux_init_cache (ElfW(auxv_t) *av)
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{
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for (; av->a_type != AT_NULL; ++av)
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switch (av->a_type)
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{
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case AT_DCACHEBSIZE:
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{
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int *cls = & __cache_line_size;
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if (cls != NULL)
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*cls = av->a_un.a_val;
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}
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break;
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}
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}
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int
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/* GKM FIXME: GCC: this should get __BP_ prefix by virtue of the
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BPs in the arglist of startup_info.main and startup_info.init. */
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BP_SYM (__libc_start_main) (int argc, char *__unbounded *__unbounded ubp_av,
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char *__unbounded *__unbounded ubp_ev,
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void *__unbounded auxvec, void (*rtld_fini) (void),
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ElfW(auxv_t) *__unbounded auxvec, void (*rtld_fini) (void),
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struct startup_info *__unbounded stinfo,
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char *__unbounded *__unbounded stack_on_entry)
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{
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@ -66,16 +91,19 @@ BP_SYM (__libc_start_main) (int argc, char *__unbounded *__unbounded ubp_av,
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as a statically-linked program by Linux... */
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if (*stack_on_entry != NULL)
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{
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char *__unbounded *__unbounded temp;
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/* ...in which case, we have argc as the top thing on the
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stack, followed by argv (NULL-terminated), envp (likewise),
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and the auxilary vector. */
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argc = *(int *__unbounded) stack_on_entry;
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ubp_av = stack_on_entry + 1;
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ubp_ev = ubp_av + argc + 1;
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auxvec = ubp_ev;
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while (*(char *__unbounded *__unbounded) auxvec != NULL)
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++auxvec;
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++auxvec;
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temp = ubp_ev;
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while (*temp != NULL)
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++temp;
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auxvec = (ElfW(auxv_t) *)++temp;
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#ifndef SHARED
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_dl_aux_init ((ElfW(auxv_t) *) auxvec);
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#endif
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@ -84,6 +112,9 @@ BP_SYM (__libc_start_main) (int argc, char *__unbounded *__unbounded ubp_av,
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INIT_ARGV_and_ENVIRON;
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/* Initialize the __cache_line_size variable from the aux vector. */
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__aux_init_cache((ElfW(auxv_t) *) auxvec);
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/* Store something that has some relationship to the end of the
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stack, for backtraces. This variable should be thread-specific. */
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__libc_stack_end = stack_on_entry + 4;
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@ -1,5 +1,5 @@
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/* Optimized memset implementation for PowerPC.
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Copyright (C) 1997, 1999, 2000 Free Software Foundation, Inc.
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Copyright (C) 1997, 1999, 2000, 2002 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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@ -21,12 +21,26 @@
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#include <bp-sym.h>
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#include <bp-asm.h>
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/* Define a global static that can hold the cache line size. The
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assumption is that startup code will access the "aux vector" to
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to obtain the value set by the kernel and store it into this
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variable. */
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.globl __cache_line_size
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.section ".data","aw"
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.align 2
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.type __cache_line_size,@object
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.size __cache_line_size,4
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__cache_line_size:
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.long 0
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.section ".text"
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/* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5]));
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Returns 's'.
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The memset is done in three sizes: byte (8 bits), word (32 bits),
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cache line (256 bits). There is a special case for setting cache lines
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to 0, to take advantage of the dcbz instruction. */
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The memset is done in four sizes: byte (8 bits), word (32 bits),
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32-byte blocks (256 bits) and __cache_line_size (128, 256, 1024 bits).
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There is a special case for setting whole cache lines to 0, which
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takes advantage of the dcbz instruction. */
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EALIGN (BP_SYM (memset), 5, 1)
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@ -50,6 +64,10 @@ EALIGN (BP_SYM (memset), 5, 1)
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#define rNEG64 r8 /* constant -64 for clearing with dcbz */
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#define rNEG32 r9 /* constant -32 for clearing with dcbz */
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#define rGOT r9 /* Address of the Global Offset Table. */
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#define rCLS r8 /* Cache line size obtained from static. */
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#define rCLM r9 /* Cache line size mask to check for cache alignment. */
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#if __BOUNDED_POINTERS__
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cmplwi cr1, rRTN, 0
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CHECK_BOUNDS_BOTH_WIDE (rMEMP0, rTMP, rTMP2, rLEN)
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@ -105,7 +123,17 @@ L(caligned):
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cmplwi cr1, rCHR, 0
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clrrwi. rALIGN, rLEN, 5
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mtcrf 0x01, rLEN /* 40th instruction from .align */
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beq cr1, L(zloopstart) /* special case for clearing memory using dcbz */
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/* Check if we can use the special case for clearing memory using dcbz.
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This requires that we know the correct cache line size for this
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processor. Getting the __cache_line_size may require establishing GOT
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addressability, so branch out of line to set this up. */
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beq cr1, L(checklinesize)
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/* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.
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Can't assume that rCHR is zero or that the cache line size is either
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32-bytes or even known. */
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L(nondcbz):
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srwi rTMP, rALIGN, 5
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mtctr rTMP
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beq L(medium) /* we may not actually get to do a full line */
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@ -114,7 +142,9 @@ L(caligned):
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li rNEG64, -0x40
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bdz L(cloopdone) /* 48th instruction from .align */
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L(c3): dcbz rNEG64, rMEMP
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/* We can't use dcbz here as we don't know the cache line size. We can
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use "data cache block touch for store", which is safe. */
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L(c3): dcbtst rNEG64, rMEMP
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stw rCHR, -4(rMEMP)
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stw rCHR, -8(rMEMP)
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stw rCHR, -12(rMEMP)
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@ -142,7 +172,10 @@ L(cloopdone):
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.align 5
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nop
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/* Clear lines of memory in 128-byte chunks. */
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/* Clear cache lines of memory in 128-byte chunks.
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This code is optimized for processors with 32-byte cache lines.
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It is further optimized for the 601 processor, which requires
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some care in how the code is aligned in the i-cache. */
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L(zloopstart):
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clrlwi rLEN, rLEN, 27
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mtcrf 0x02, rALIGN
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@ -226,4 +259,80 @@ L(medium_28t):
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stw rCHR, -4(rMEMP)
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stw rCHR, -8(rMEMP)
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blr
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L(checklinesize):
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#ifdef SHARED
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mflr rTMP
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/* If the remaining length is less the 32 bytes then don't bother getting
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the cache line size. */
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beq L(medium)
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/* Establishes GOT addressability so we can load __cache_line_size
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from static. This value was set from the aux vector during startup. */
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bl _GLOBAL_OFFSET_TABLE_@local-4
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mflr rGOT
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lwz rGOT,__cache_line_size@got(rGOT)
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lwz rCLS,0(rGOT)
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mtlr rTMP
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#else
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/* Load __cache_line_size from static. This value was set from the
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aux vector during startup. */
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lis rCLS,__cache_line_size@ha
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/* If the remaining length is less the 32 bytes then don't bother getting
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the cache line size. */
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beq L(medium)
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lwz rCLS,__cache_line_size@l(rCLS)
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#endif
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/*If the cache line size was not set then goto to L(nondcbz), which is
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safe for any cache line size. */
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cmplwi cr1,rCLS,0
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beq cr1,L(nondcbz)
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/* If the cache line size is 32 bytes then goto to L(zloopstart),
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which is coded specificly for 32-byte lines (and 601). */
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cmplwi cr1,rCLS,32
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beq cr1,L(zloopstart)
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/* Now we know the cache line size and it is not 32-bytes. However
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we may not yet be aligned to the cache line and may have a partial
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line to fill. Touch it 1st to fetch the cache line. */
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dcbtst 0,rMEMP
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addi rCLM,rCLS,-1
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L(getCacheAligned):
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cmplwi cr1,rLEN,32
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and. rTMP,rCLM,rMEMP
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blt cr1,L(handletail32)
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beq L(cacheAligned)
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/* We are not aligned to start of a cache line yet. Store 32-byte
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of data and test again. */
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addi rMEMP,rMEMP,32
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addi rLEN,rLEN,-32
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stw rCHR,-32(rMEMP)
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stw rCHR,-28(rMEMP)
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stw rCHR,-24(rMEMP)
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stw rCHR,-20(rMEMP)
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stw rCHR,-16(rMEMP)
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stw rCHR,-12(rMEMP)
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stw rCHR,-8(rMEMP)
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stw rCHR,-4(rMEMP)
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b L(getCacheAligned)
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/* Now we are aligned to the cache line and can use dcbz. */
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L(cacheAligned):
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cmplw cr1,rLEN,rCLS
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blt cr1,L(handletail32)
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dcbz 0,rMEMP
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subf rLEN,rCLS,rLEN
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add rMEMP,rMEMP,rCLS
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b L(cacheAligned)
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/* We are here because; the cache line size was set, it was not
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32-bytes, and the remainder (rLEN) is now less than the actual cache
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line size. Set up the preconditions for L(nondcbz) and go there to
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store the remaining bytes. */
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L(handletail32):
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clrrwi. rALIGN, rLEN, 5
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b L(nondcbz)
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END (BP_SYM (memset))
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@ -20,6 +20,32 @@
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#include "config.h"
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#include "kernel-features.h"
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#include <ldsodefs.h>
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extern int __cache_line_size;
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weak_extern (__cache_line_size)
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#define DL_PLATFORM_INIT __aux_init_cache(_dl_auxv)
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/* Scan the Aux Vector for the "Data Cache Block Size" entry. If found
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verify that the static extern __cache_line_size is defined by checking
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for not NULL. If it is defined then assign the cache block size
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value to __cache_line_size. */
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static inline void
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__aux_init_cache (ElfW(auxv_t) *av)
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{
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for (; av->a_type != AT_NULL; ++av)
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switch (av->a_type)
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{
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case AT_DCACHEBSIZE:
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{
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int *cls = & __cache_line_size;
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if (cls != NULL)
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*cls = av->a_un.a_val;
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}
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break;
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}
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}
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#ifndef __ASSUME_STD_AUXV
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