powerpc: Fix __fesetround_inline_nocheck on POWER9+ (BZ 31682)

The e68b1151f7 commit changed the
__fesetround_inline_nocheck implementation to use mffscrni
(through __fe_mffscrn) instead of mtfsfi.  For generic powerpc
ceil/floor/trunc, the function is supposed to disable the
floating-point inexact exception enable bit, however mffscrni
does not change any exception enable bits.

This patch fixes by reverting the optimization for the
__fesetround_inline_nocheck.

Checked on powerpc-linux-gnu.
Reviewed-by: Paul E. Murphy <murphyp@linux.ibm.com>
This commit is contained in:
Adhemerval Zanella 2024-05-07 09:19:48 -03:00
parent dd5f891c1a
commit ae515ba530
2 changed files with 8 additions and 14 deletions

View File

@ -182,19 +182,13 @@ __fesetround_inline (int round)
return 0;
}
/* Same as __fesetround_inline, however without runtime check to use DFP
mtfsfi syntax (as relax_fenv_state) or if round value is valid. */
/* Same as __fesetround_inline, and it also disable the floating-point
inexact execption (bit 60 - XE, assuming NI is 0). It does not check
if ROUND is a valid value. */
static inline void
__fesetround_inline_nocheck (const int round)
__fesetround_inline_disable_inexact (const int round)
{
#ifdef _ARCH_PWR9
__fe_mffscrn (round);
#else
if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
__fe_mffscrn (round);
else
asm volatile ("mtfsfi 7,%0" : : "n" (round));
#endif
asm volatile ("mtfsfi 7,%0" : : "n" (round));
}
#define FPSCR_MASK(bit) (1 << (31 - (bit)))

View File

@ -42,14 +42,14 @@ set_fenv_mode (enum round_mode mode)
switch (mode)
{
case CEIL:
__fesetround_inline_nocheck (FE_UPWARD);
__fesetround_inline_disable_inexact (FE_UPWARD);
break;
case FLOOR:
__fesetround_inline_nocheck (FE_DOWNWARD);
__fesetround_inline_disable_inexact (FE_DOWNWARD);
break;
case TRUNC:
case ROUND:
__fesetround_inline_nocheck (FE_TOWARDZERO);
__fesetround_inline_disable_inexact (FE_TOWARDZERO);
break;
case NEARBYINT:
/* Disable FE_INEXACT exception */