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i486 specific atomic operations.
This commit is contained in:
Ulrich Drepper
parent
b15c9395a8
commit
b1473c3238
340
nptl/sysdeps/i386/i486/bits/atomic.h
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340
nptl/sysdeps/i386/i486/bits/atomic.h
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/* Copyright (C) 2002 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <stdint.h>
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int16_t atomic16_t;
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typedef uint16_t uatomic16_t;
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typedef int_fast16_t atomic_fast16_t;
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typedef uint_fast16_t uatomic_fast16_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#ifndef LOCK
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# ifdef UP
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# define LOCK /* nothing */
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# else
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# define LOCK "lock;"
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# endif
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#endif
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#define __arch_compare_and_exchange_8_acq(mem, newval, oldval) \
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({ unsigned char ret; \
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__asm __volatile (LOCK "cmpxchgb %b2, %1; setne %0" \
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: "=a" (ret), "=m" (*mem) \
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: "q" (newval), "1" (*mem), "0" (oldval)); \
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ret; })
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#define __arch_compare_and_exchange_16_acq(mem, newval, oldval) \
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({ unsigned char ret; \
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__asm __volatile (LOCK "cmpxchgw %w2, %1; setne %0" \
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: "=a" (ret), "=m" (*mem) \
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: "r" (newval), "1" (*mem), "0" (oldval)); \
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ret; })
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#define __arch_compare_and_exchange_32_acq(mem, newval, oldval) \
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({ unsigned char ret; \
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__asm __volatile (LOCK "cmpxchgl %2, %1; setne %0" \
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: "=a" (ret), "=m" (*mem) \
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: "r" (newval), "1" (*mem), "0" (oldval)); \
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ret; })
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/* XXX We do not really need 64-bit compare-and-exchange. At least
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not in the moment. Using it would mean causing portability
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problems since not many other 32-bit architectures have support for
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such an operation. So don't define any code for now. If it is
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really going to be used the code below can be used. */
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#if 1
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# define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
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(abort (), 0)
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#else
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# ifdef __PIC__
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# define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
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({ unsigned char ret; \
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int ignore; \
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__asm __volatile ("xchgl %3, %%ebx\n\t" \
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LOCK "cmpxchg8b %2, %1\n\t" \
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"setne %0\n\t" \
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"xchgl %3, %%ebx" \
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: "=a" (ret), "=m" (*mem), "=d" (ignore) \
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: "DS" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"1" (*mem), "0" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"2" (((unsigned long long int) (oldval)) >> 32)); \
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ret; })
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# else
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# define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
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({ unsigned char ret; \
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int ignore; \
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__asm __volatile (LOCK "cmpxchg8b %2, %1; setne %0" \
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: "=a" (ret), "=m" (*mem), "=d" (ignore) \
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: "b" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"1" (*mem), "0" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"2" (((unsigned long long int) (oldval)) >> 32)); \
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ret; })
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# endif
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#endif
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#define atomic_exchange_and_add(mem, value) \
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({ __typeof (*mem) result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "xaddb %b0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (value), "1" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "xaddw %w0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (value), "1" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "xaddl %0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (value), "1" (*mem)); \
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else \
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{ \
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__typeof (value) addval = (value); \
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__typeof (*mem) oldval; \
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__typeof (mem) memp = (mem); \
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do \
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result = (oldval = *memp) + addval; \
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while (! __arch_compare_and_exchange_64_acq (memp, result, oldval)); \
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} \
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result; })
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#define atomic_add(mem, value) \
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(void) ({ if (__builtin_constant_p (value) && (value) == 1) \
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atomic_increment (mem); \
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else if (__builtin_constant_p (value) && (value) == 1) \
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atomic_decrement (mem); \
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else if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "addb %b1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "addw %w1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "addl %1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "0" (*mem)); \
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else \
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{ \
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__typeof (value) addval = (value); \
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__typeof (*mem) oldval; \
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__typeof (mem) memp = (mem); \
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do \
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oldval = *memp; \
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while (! __arch_compare_and_exchange_64_acq (memp, \
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oldval + addval, \
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oldval)); \
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} \
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})
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#define atomic_add_negative(mem, value) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "addb %b2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "iq" (value), "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "addw %w2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "addl %2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "0" (*mem)); \
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else \
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abort (); \
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__result; })
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#define atomic_add_zero(mem, value) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "addb %b2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "addw %w2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "addl %2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "0" (*mem)); \
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else \
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abort (); \
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__result; })
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#define atomic_increment(mem) \
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(void) ({ if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "incb %b0" \
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: "=m" (*mem) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "incw %w0" \
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: "=m" (*mem) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "incl %0" \
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: "=m" (*mem) \
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: "0" (*mem)); \
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else \
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{ \
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__typeof (*mem) oldval; \
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__typeof (mem) memp = (mem); \
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do \
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oldval = *memp; \
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while (! __arch_compare_and_exchange_64_acq (memp, \
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oldval + 1, \
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oldval)); \
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} \
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})
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#define atomic_increment_and_test(mem) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "incb %0; sete %b1" \
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: "=m" (*mem), "=qm" (__result) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "incw %0; sete %w1" \
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: "=m" (*mem), "=qm" (__result) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "incl %0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "0" (*mem)); \
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else \
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abort (); \
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__result; })
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#define atomic_decrement(mem) \
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(void) ({ if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "decb %b0" \
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: "=m" (*mem) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "decw %w0" \
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: "=m" (*mem) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "decl %0" \
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: "=m" (*mem) \
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: "0" (*mem)); \
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else \
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{ \
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__typeof (*mem) oldval; \
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__typeof (mem) memp = (mem); \
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do \
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oldval = *memp; \
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while (! __arch_compare_and_exchange_64_acq (memp, \
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oldval - 1, \
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oldval)); \
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} \
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})
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#define atomic_decrement_and_test(mem) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "decb %b0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "decw %w0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "0" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "decl %0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "0" (*mem)); \
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else \
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abort (); \
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__result; })
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#define atomic_bit_set(mem, bit) \
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(void) ({ if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "orb %b2, %0" \
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: "=m" (*mem) \
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: "0" (*mem), "i" (1 << (bit))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "orw %w2, %0" \
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: "=m" (*mem) \
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: "0" (*mem), "i" (1 << (bit))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "orl %2, %0" \
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: "=m" (*mem) \
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: "0" (*mem), "i" (1 << (bit))); \
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else \
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abort (); \
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})
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#define atomic_bit_test_set(mem, bit) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK "btsb %3, %1; setc %0" \
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: "=q" (__result), "=m" (*mem) \
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: "1" (*mem), "i" (bit)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK "btsw %3, %1; setc %0" \
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: "=q" (__result), "=m" (*mem) \
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: "1" (*mem), "i" (bit)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK "btsl %3, %1; setc %0" \
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: "=q" (__result), "=m" (*mem) \
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: "1" (*mem), "i" (bit)); \
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else \
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abort (); \
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__result; })
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