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https://sourceware.org/git/glibc.git
synced 2025-01-13 04:30:07 +00:00
x86_64: Add avx2 optimized __memcmpeq in memcmpeq-avx2.S
No bug. This commit adds new optimized __memcmpeq implementation for avx2. The primary optimizations are: 1) skipping the logic to find the difference of the first mismatched byte. 2) not updating src/dst addresses as the non-equals logic does not need to be reused by different areas.
This commit is contained in:
Noah Goldstein
parent
fa7f63d8d6
commit
b4ed69ba16
@ -42,13 +42,11 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL (i, name, __memcmpeq,
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IFUNC_IMPL_ADD (array, i, __memcmpeq,
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(CPU_FEATURE_USABLE (AVX2)
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&& CPU_FEATURE_USABLE (MOVBE)
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&& CPU_FEATURE_USABLE (BMI2)),
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__memcmpeq_avx2)
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IFUNC_IMPL_ADD (array, i, __memcmpeq,
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(CPU_FEATURE_USABLE (AVX2)
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&& CPU_FEATURE_USABLE (BMI2)
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&& CPU_FEATURE_USABLE (MOVBE)
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&& CPU_FEATURE_USABLE (RTM)),
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__memcmpeq_avx2_rtm)
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IFUNC_IMPL_ADD (array, i, __memcmpeq,
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@ -31,10 +31,10 @@ IFUNC_SELECTOR (void)
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
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&& CPU_FEATURE_USABLE_P (cpu_features, BMI2)
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&& CPU_FEATURE_USABLE_P (cpu_features, MOVBE)
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&& CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
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{
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
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&& CPU_FEATURE_USABLE_P (cpu_features, MOVBE)
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&& CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
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return OPTIMIZE1 (evex);
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@ -1,5 +1,5 @@
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#ifndef MEMCMP
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# define MEMCMP __memcmpeq_avx2_rtm
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#ifndef MEMCMPEQ
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# define MEMCMPEQ __memcmpeq_avx2_rtm
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#endif
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#define ZERO_UPPER_VEC_REGISTERS_RETURN \
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@ -16,8 +16,309 @@
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef MEMCMP
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# define MEMCMP __memcmpeq_avx2
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#endif
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#if IS_IN (libc)
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#include "memcmp-avx2-movbe.S"
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/* __memcmpeq is implemented as:
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1. Use ymm vector compares when possible. The only case where
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vector compares is not possible for when size < VEC_SIZE
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and loading from either s1 or s2 would cause a page cross.
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2. Use xmm vector compare when size >= 8 bytes.
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3. Optimistically compare up to first 4 * VEC_SIZE one at a
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to check for early mismatches. Only do this if its guranteed the
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work is not wasted.
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4. If size is 8 * VEC_SIZE or less, unroll the loop.
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5. Compare 4 * VEC_SIZE at a time with the aligned first memory
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area.
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6. Use 2 vector compares when size is 2 * VEC_SIZE or less.
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7. Use 4 vector compares when size is 4 * VEC_SIZE or less.
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8. Use 8 vector compares when size is 8 * VEC_SIZE or less. */
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# include <sysdep.h>
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# ifndef MEMCMPEQ
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# define MEMCMPEQ __memcmpeq_avx2
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# endif
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# define VPCMPEQ vpcmpeqb
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# ifndef VZEROUPPER
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# define VZEROUPPER vzeroupper
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# endif
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# ifndef SECTION
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# define SECTION(p) p##.avx
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# endif
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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.section SECTION(.text), "ax", @progbits
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ENTRY_P2ALIGN (MEMCMPEQ, 6)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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jb L(less_vec)
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/* From VEC to 2 * VEC. No branch when size == VEC_SIZE. */
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vmovdqu (%rsi), %ymm1
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VPCMPEQ (%rdi), %ymm1, %ymm1
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vpmovmskb %ymm1, %eax
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incl %eax
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jnz L(return_neq0)
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cmpq $(VEC_SIZE * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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vmovdqu VEC_SIZE(%rsi), %ymm2
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VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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vpmovmskb %ymm2, %eax
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/* If all 4 VEC where equal eax will be all 1s so incl will overflow
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and set zero flag. */
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incl %eax
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jnz L(return_neq0)
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/* Less than 4 * VEC. */
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vpmovmskb %ymm3, %eax
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incl %eax
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jnz L(return_neq0)
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vmovdqu (VEC_SIZE * 3)(%rsi), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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vpmovmskb %ymm4, %eax
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incl %eax
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jnz L(return_neq0)
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/* Go to 4x VEC loop. */
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cmpq $(VEC_SIZE * 8), %rdx
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ja L(more_8x_vec)
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/* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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branches. */
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/* Adjust rsi and rdi to avoid indexed address mode. This end up
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saving a 16 bytes of code, prevents unlamination, and bottlenecks in
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the AGU. */
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addq %rdx, %rsi
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vmovdqu -(VEC_SIZE * 4)(%rsi), %ymm1
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vmovdqu -(VEC_SIZE * 3)(%rsi), %ymm2
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addq %rdx, %rdi
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VPCMPEQ -(VEC_SIZE * 4)(%rdi), %ymm1, %ymm1
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VPCMPEQ -(VEC_SIZE * 3)(%rdi), %ymm2, %ymm2
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vmovdqu -(VEC_SIZE * 2)(%rsi), %ymm3
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VPCMPEQ -(VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vmovdqu -VEC_SIZE(%rsi), %ymm4
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VPCMPEQ -VEC_SIZE(%rdi), %ymm4, %ymm4
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/* Reduce VEC0 - VEC4. */
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vpand %ymm1, %ymm2, %ymm2
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vpand %ymm3, %ymm4, %ymm4
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vpand %ymm2, %ymm4, %ymm4
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vpmovmskb %ymm4, %eax
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incl %eax
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L(return_neq0):
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L(return_vzeroupper):
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ZERO_UPPER_VEC_REGISTERS_RETURN
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/* NB: p2align 5 here will ensure the L(loop_4x_vec) is also 32 byte
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aligned. */
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.p2align 5
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L(less_vec):
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/* Check if one or less char. This is necessary for size = 0 but is
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also faster for size = 1. */
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cmpl $1, %edx
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jbe L(one_or_less)
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/* Check if loading one VEC from either s1 or s2 could cause a page
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cross. This can have false positives but is by far the fastest
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method. */
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movl %edi, %eax
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orl %esi, %eax
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andl $(PAGE_SIZE - 1), %eax
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cmpl $(PAGE_SIZE - VEC_SIZE), %eax
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jg L(page_cross_less_vec)
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/* No page cross possible. */
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vmovdqu (%rsi), %ymm2
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VPCMPEQ (%rdi), %ymm2, %ymm2
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vpmovmskb %ymm2, %eax
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incl %eax
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/* Result will be zero if s1 and s2 match. Otherwise first set bit
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will be first mismatch. */
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bzhil %edx, %eax, %eax
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VZEROUPPER_RETURN
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/* Relatively cold but placing close to L(less_vec) for 2 byte jump
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encoding. */
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.p2align 4
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L(one_or_less):
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jb L(zero)
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movzbl (%rsi), %ecx
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movzbl (%rdi), %eax
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subl %ecx, %eax
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/* No ymm register was touched. */
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ret
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/* Within the same 16 byte block is L(one_or_less). */
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L(zero):
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xorl %eax, %eax
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ret
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.p2align 4
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L(last_1x_vec):
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vmovdqu -(VEC_SIZE * 1)(%rsi, %rdx), %ymm1
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VPCMPEQ -(VEC_SIZE * 1)(%rdi, %rdx), %ymm1, %ymm1
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vpmovmskb %ymm1, %eax
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incl %eax
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VZEROUPPER_RETURN
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.p2align 4
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L(last_2x_vec):
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vmovdqu -(VEC_SIZE * 2)(%rsi, %rdx), %ymm1
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VPCMPEQ -(VEC_SIZE * 2)(%rdi, %rdx), %ymm1, %ymm1
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vmovdqu -(VEC_SIZE * 1)(%rsi, %rdx), %ymm2
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VPCMPEQ -(VEC_SIZE * 1)(%rdi, %rdx), %ymm2, %ymm2
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vpand %ymm1, %ymm2, %ymm2
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vpmovmskb %ymm2, %eax
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incl %eax
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VZEROUPPER_RETURN
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.p2align 4
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx), %rdx
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/* rsi stores s2 - s1. This allows loop to only update one pointer.
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*/
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subq %rdi, %rsi
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/* Align s1 pointer. */
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andq $-VEC_SIZE, %rdi
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/* Adjust because first 4x vec where check already. */
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subq $-(VEC_SIZE * 4), %rdi
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.p2align 4
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L(loop_4x_vec):
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/* rsi has s2 - s1 so get correct address by adding s1 (in rdi). */
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vmovdqu (%rsi, %rdi), %ymm1
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VPCMPEQ (%rdi), %ymm1, %ymm1
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vmovdqu VEC_SIZE(%rsi, %rdi), %ymm2
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VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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vmovdqu (VEC_SIZE * 2)(%rsi, %rdi), %ymm3
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vmovdqu (VEC_SIZE * 3)(%rsi, %rdi), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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vpand %ymm1, %ymm2, %ymm2
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vpand %ymm3, %ymm4, %ymm4
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vpand %ymm2, %ymm4, %ymm4
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vpmovmskb %ymm4, %eax
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incl %eax
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jnz L(return_neq1)
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subq $-(VEC_SIZE * 4), %rdi
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/* Check if s1 pointer at end. */
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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vmovdqu (VEC_SIZE * 3)(%rsi, %rdx), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdx), %ymm4, %ymm4
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subq %rdx, %rdi
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/* rdi has 4 * VEC_SIZE - remaining length. */
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cmpl $(VEC_SIZE * 3), %edi
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jae L(8x_last_1x_vec)
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/* Load regardless of branch. */
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vmovdqu (VEC_SIZE * 2)(%rsi, %rdx), %ymm3
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VPCMPEQ (VEC_SIZE * 2)(%rdx), %ymm3, %ymm3
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cmpl $(VEC_SIZE * 2), %edi
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jae L(8x_last_2x_vec)
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/* Check last 4 VEC. */
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vmovdqu VEC_SIZE(%rsi, %rdx), %ymm1
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VPCMPEQ VEC_SIZE(%rdx), %ymm1, %ymm1
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vmovdqu (%rsi, %rdx), %ymm2
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VPCMPEQ (%rdx), %ymm2, %ymm2
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vpand %ymm3, %ymm4, %ymm4
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vpand %ymm1, %ymm2, %ymm3
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L(8x_last_2x_vec):
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vpand %ymm3, %ymm4, %ymm4
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L(8x_last_1x_vec):
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vpmovmskb %ymm4, %eax
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/* Restore s1 pointer to rdi. */
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incl %eax
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L(return_neq1):
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VZEROUPPER_RETURN
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/* Relatively cold case as page cross are unexpected. */
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.p2align 4
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L(page_cross_less_vec):
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cmpl $16, %edx
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jae L(between_16_31)
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cmpl $8, %edx
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ja L(between_9_15)
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cmpl $4, %edx
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jb L(between_2_3)
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/* From 4 to 8 bytes. No branch when size == 4. */
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movl (%rdi), %eax
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subl (%rsi), %eax
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movl -4(%rdi, %rdx), %ecx
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movl -4(%rsi, %rdx), %edi
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subl %edi, %ecx
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orl %ecx, %eax
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ret
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.p2align 4,, 8
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L(between_16_31):
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/* From 16 to 31 bytes. No branch when size == 16. */
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/* Safe to use xmm[0, 15] as no vzeroupper is needed so RTM safe.
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*/
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vmovdqu (%rsi), %xmm1
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vpcmpeqb (%rdi), %xmm1, %xmm1
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vmovdqu -16(%rsi, %rdx), %xmm2
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vpcmpeqb -16(%rdi, %rdx), %xmm2, %xmm2
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vpand %xmm1, %xmm2, %xmm2
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vpmovmskb %xmm2, %eax
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notw %ax
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/* No ymm register was touched. */
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ret
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.p2align 4,, 8
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L(between_9_15):
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/* From 9 to 15 bytes. */
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movq (%rdi), %rax
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subq (%rsi), %rax
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movq -8(%rdi, %rdx), %rcx
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movq -8(%rsi, %rdx), %rdi
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subq %rdi, %rcx
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orq %rcx, %rax
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/* edx is guranteed to be a non-zero int. */
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cmovnz %edx, %eax
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ret
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/* Don't align. This is cold and aligning here will cause code
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to spill into next cache line. */
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L(between_2_3):
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/* From 2 to 3 bytes. No branch when size == 2. */
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movzwl (%rdi), %eax
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movzwl (%rsi), %ecx
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subl %ecx, %eax
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movzbl -1(%rdi, %rdx), %ecx
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/* All machines that support evex will insert a "merging uop"
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avoiding any serious partial register stalls. */
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subb -1(%rsi, %rdx), %cl
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orl %ecx, %eax
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/* No ymm register was touched. */
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ret
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/* 2 Bytes from next cache line. */
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END (MEMCMPEQ)
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#endif
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