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Update.
* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask. * sysdeps/i386/fpu/feenablxcpt.c: Likewise. * sysdeps/i386/fpu/feholdexcpt.c: Likewise. * sysdeps/i386/fpu/fesetround.c: Likewise. * sysdeps/i386/fpu/ftestexcept.c: Likewise.
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@ -6,6 +6,12 @@
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which has undefined symbols.
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* elf/Makefile: Likewise.
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* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask.
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* sysdeps/i386/fpu/feenablxcpt.c: Likewise.
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* sysdeps/i386/fpu/feholdexcpt.c: Likewise.
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* sysdeps/i386/fpu/fesetround.c: Likewise.
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* sysdeps/i386/fpu/ftestexcept.c: Likewise.
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2003-07-21 HJ Lu <hongjiu.lu@intel.com>
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* elf/ldconfig.c (search_dir): Treat symlink as regular file
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@ -39,7 +39,7 @@ fedisableexcept (int excepts)
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__asm__ ("fldcw %0" : : "m" (*&new_exc));
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/* If the CPU supports SSE we set the MXCSR as well. */
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if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
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if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
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{
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unsigned int xnew_exc;
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@ -39,7 +39,7 @@ feenableexcept (int excepts)
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__asm__ ("fldcw %0" : : "m" (*&new_exc));
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/* If the CPU supports SSE we set the MXCSR as well. */
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if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
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if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
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{
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unsigned int xnew_exc;
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@ -36,7 +36,7 @@ feholdexcept (fenv_t *envp)
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__asm__ ("fldcw %0" : : "m" (*&work));
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/* If the CPU supports SSE we set the MXCSR as well. */
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if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
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if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
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{
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unsigned int xwork;
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@ -38,7 +38,7 @@ fesetround (int round)
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__asm__ ("fldcw %0" : : "m" (*&cw));
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/* If the CPU supports SSE we set the MXCSR as well. */
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if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
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if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
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{
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unsigned int xcw;
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@ -33,7 +33,7 @@ fetestexcept (int excepts)
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__asm__ ("fnstsw %0" : "=a" (temp));
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/* If the CPU supports SSE we test the MXCSR as well. */
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if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
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if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
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__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
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return (temp | xtemp) & excepts & FE_ALL_EXCEPT;
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