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* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask.
	* sysdeps/i386/fpu/feenablxcpt.c: Likewise.
	* sysdeps/i386/fpu/feholdexcpt.c: Likewise.
	* sysdeps/i386/fpu/fesetround.c: Likewise.
	* sysdeps/i386/fpu/ftestexcept.c: Likewise.
This commit is contained in:
Ulrich Drepper 2003-07-22 00:14:36 +00:00
parent 1a379ea0c7
commit b72e048f19
6 changed files with 11 additions and 5 deletions
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6
ChangeLog
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@ -6,6 +6,12 @@
which has undefined symbols.
* elf/Makefile: Likewise.
* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask.
* sysdeps/i386/fpu/feenablxcpt.c: Likewise.
* sysdeps/i386/fpu/feholdexcpt.c: Likewise.
* sysdeps/i386/fpu/fesetround.c: Likewise.
* sysdeps/i386/fpu/ftestexcept.c: Likewise.
2003-07-21 HJ Lu <hongjiu.lu@intel.com>
* elf/ldconfig.c (search_dir): Treat symlink as regular file

2
sysdeps/i386/fpu/fedisblxcpt.c
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@ -39,7 +39,7 @@ fedisableexcept (int excepts)
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xnew_exc;

2
sysdeps/i386/fpu/feenablxcpt.c
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@ -39,7 +39,7 @@ feenableexcept (int excepts)
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xnew_exc;

2
sysdeps/i386/fpu/feholdexcpt.c
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@ -36,7 +36,7 @@ feholdexcept (fenv_t *envp)
__asm__ ("fldcw %0" : : "m" (*&work));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xwork;

2
sysdeps/i386/fpu/fesetround.c
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@ -38,7 +38,7 @@ fesetround (int round)
__asm__ ("fldcw %0" : : "m" (*&cw));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xcw;

2
sysdeps/i386/fpu/ftestexcept.c
View File

@ -33,7 +33,7 @@ fetestexcept (int excepts)
__asm__ ("fnstsw %0" : "=a" (temp));
/* If the CPU supports SSE we test the MXCSR as well. */
if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
return (temp | xtemp) & excepts & FE_ALL_EXCEPT;