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* sysdeps/powerpc/bits/link.h (La_ppc64_regs): Add lr_vrsave.
(La_ppc64_retval): Correct size of lrc_fp. * sysdeps/powerpc/powerpc64/dl-trampoline.S (_dl_profile_resolve): Fix up ABI problems and complete function.
This commit is contained in:
Ulrich Drepper
parent
88764ae26a
commit
bb4bb82b13
@ -1,3 +1,10 @@
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2005-02-07 Steven Munroe <sjmunroe@us.ibm.com>
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* sysdeps/powerpc/bits/link.h (La_ppc64_regs): Add lr_vrsave.
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(La_ppc64_retval): Correct size of lrc_fp.
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* sysdeps/powerpc/powerpc64/dl-trampoline.S (_dl_profile_resolve):
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Fix up ABI problems and complete function.
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2005-03-10 Jakub Jelinek <jakub@redhat.com>
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2005-03-10 Jakub Jelinek <jakub@redhat.com>
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* math/test-misc.c (main): Add some more tests.
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* math/test-misc.c (main): Add some more tests.
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@ -71,7 +71,8 @@ typedef struct La_ppc64_regs
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{
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{
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uint64_t lr_reg[8];
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uint64_t lr_reg[8];
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double lr_fp[13];
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double lr_fp[13];
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uint64_t __padding;
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uint32_t __padding;
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uint32_t lr_vrsave;
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uint32_t lr_vreg[12][4];
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uint32_t lr_vreg[12][4];
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uint64_t lr_r1;
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uint64_t lr_r1;
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uint64_t lr_lr;
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uint64_t lr_lr;
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@ -82,8 +83,8 @@ typedef struct La_ppc64_retval
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{
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{
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uint64_t lrv_r3;
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uint64_t lrv_r3;
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uint64_t lrv_r4;
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uint64_t lrv_r4;
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double lrv_fp[8];
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double lrv_fp[4]; /* f1-f4, float - complex long double. */
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uint32_t lrv_v2[4];
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uint32_t lrv_v2[4]; /* v2. */
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} La_ppc64_retval;
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} La_ppc64_retval;
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@ -18,8 +18,14 @@
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02111-1307 USA. */
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02111-1307 USA. */
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#include <sysdep.h>
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#include <sysdep.h>
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#include <rtld-global-offsets.h>
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.section ".text"
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.section ".text"
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/* On entry r0 contains the index of the PLT entry we need to fixup
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and r11 contains the link_map (from PLT0+16). The link_map becomes
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parm1 (r3) and the index (r0) need to be converted to an offset
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(index * 24) in parm2 (r4). */
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EALIGN(_dl_runtime_resolve, 4, 0)
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EALIGN(_dl_runtime_resolve, 4, 0)
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/* We need to save the registers used to pass parameters, ie. r3 thru
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/* We need to save the registers used to pass parameters, ie. r3 thru
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@ -68,129 +74,362 @@ EALIGN(_dl_runtime_resolve, 4, 0)
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bctr
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bctr
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END(_dl_runtime_resolve)
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END(_dl_runtime_resolve)
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/* Stack layout:
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+592 previous backchain
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+584 spill_r31
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+576 spill_r30
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+560 v1
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+552 fp4
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+544 fp3
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+536 fp2
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+528 fp1
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+520 r4
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+512 r3
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return values
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+504 free
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+496 stackframe
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+488 lr
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+480 r1
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+464 v13
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+448 v12
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+432 v11
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+416 v10
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+400 v9
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+384 v8
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+368 v7
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+352 v6
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+336 v5
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+320 v4
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+304 v3
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+288 v2
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* VMX Parms in V2-V13, V0-V1 are scratch
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+284 vrsave
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+280 free
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+272 fp13
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+264 fp12
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+256 fp11
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+248 fp10
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+240 fp9
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+232 fp8
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+224 fp7
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+216 fp6
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+208 fp5
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+200 fp4
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+192 fp3
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+184 fp2
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+176 fp1
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* FP Parms in FP1-FP13, FP0 is a scratch register
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+168 r10
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+160 r9
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+152 r8
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+144 r7
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+136 r6
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+128 r5
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+120 r4
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+112 r3
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* Integer parms in R3-R10, R0 is scratch, R1 SP, R2 is TOC
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+104 parm8
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+96 parm7
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+88 parm6
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+80 parm5
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+72 parm4
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+64 parm3
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+56 parm2
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+48 parm1
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* Parameter save area, Allocated by the call, at least 8 double words
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+40 TOC save area
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+32 Reserved for linker
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+24 Reserved for compiler
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+16 LR save area
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+8 CR save area
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r1+0 stack back chain
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*/
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#define FRAME_SIZE 592
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#define INT_RTN 512
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#define FPR_RTN 528
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#define VR_RTN 560
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#define STACK_FRAME 496
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#define CALLING_LR 488
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#define CALLING_SP 480
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#define INT_PARMS 112
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#define FPR_PARMS 176
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#define VR_PARMS 288
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#define VR_VRSAVE 284
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.section ".toc","aw"
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.LC__dl_hwcap:
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# ifdef SHARED
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.tc _rtld_global_ro[TC],_rtld_global_ro
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# else
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.tc _dl_hwcap[TC],_dl_hwcap
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# endif
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.section ".text"
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.machine "altivec"
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/* On entry r0 contains the index of the PLT entry we need to fixup
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and r11 contains the link_map (from PLT0+16). The link_map becomes
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parm1 (r3) and the index (r0) needs to be converted to an offset
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(index * 24) in parm2 (r4). */
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EALIGN(_dl_profile_resolve, 4, 0)
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EALIGN(_dl_profile_resolve, 4, 0)
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/* Spill r30, r31 to preserve the link_map* and reloc_addr, in case we
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need to call _dl_call_pltexit. */
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std r31,-8(r1)
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std r30,-16(r1)
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/* We need to save the registers used to pass parameters, ie. r3 thru
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/* We need to save the registers used to pass parameters, ie. r3 thru
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r10; the registers are saved in a stack frame. */
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r10; the registers are saved in a stack frame. */
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stdu r1,-448(r1)
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stdu r1,-FRAME_SIZE(r1)
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/* Stack layout:
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std r3,INT_PARMS+0(r1)
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+432 stackframe
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+424 lr
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+416 r1
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+400 v12
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+384 v11
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+368 v10
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+362 v9
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+336 v8
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+320 v7
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+304 v6
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+288 v5
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+272 v4
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+256 v3
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+240 v2
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+224 v1
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+216 free
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+208 fp13
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+200 fp12
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+192 fp11
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+184 fp10
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+176 fp9
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+168 fp8
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+160 fp7
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+152 fp6
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+144 fp5
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+136 fp4
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+128 fp3
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+120 fp2
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+112 fp1
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+104 r10
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+96 r9
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+88 r8
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+80 r7
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+72 r6
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+64 r5
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+56 r4
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+48 r3
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+8 cr
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r1 link
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*/
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std r3,48(r1)
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mr r3,r11
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mr r3,r11
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std r4,56(r1)
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std r4,INT_PARMS+8(r1)
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sldi r4,r0,1
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sldi r4,r0,1 /* index * 2 */
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std r5,64(r1)
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std r5,INT_PARMS+16(r1)
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add r4,r4,0
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add r4,r4,r0 /* index * 3 */
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std r6,72(r1)
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std r6,INT_PARMS+24(r1)
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sldi r4,r4,3
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sldi r4,r4,3 /* index * 24 == PLT offset */
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std r7,80(r1)
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mflr r5
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mflr r5
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std r8,88(r1)
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std r7,INT_PARMS+32(r1)
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std r8,INT_PARMS+40(r1)
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/* Store the LR in the LR Save area of the previous frame. */
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/* Store the LR in the LR Save area of the previous frame. */
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/* XXX Do we have to do this? */
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/* XXX Do we have to do this? */
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std r5,448+16(r1)
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la r8,FRAME_SIZE(r1)
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std r5,424(r1)
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std r5,FRAME_SIZE+16(r1)
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std r5,CALLING_LR(r1)
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mfcr r0
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mfcr r0
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std r9,96(r1)
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std r9,INT_PARMS+48(r1)
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std r10,104(r1)
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std r10,INT_PARMS+56(r1)
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std r8,CALLING_SP(r1)
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/* I'm almost certain we don't have to save cr... be safe. */
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/* I'm almost certain we don't have to save cr... be safe. */
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std r0,8(r1)
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std r0,8(r1)
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ld r12,.LC__dl_hwcap@toc(r2)
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#ifdef SHARED
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/* Load _rtld-global._dl_hwcap. */
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ld r12,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r12)
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#else
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ld r12,0(r12) /* Load extern _dl_hwcap. */
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#endif
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andis. r0,r12,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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beq L(saveFP)
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la r10,(VR_PARMS+0)(r1)
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la r9,(VR_PARMS+16)(r1)
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li r11,32
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li r12,64
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stvx v2,0,r10
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stvx v3,0,r9
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stvx v4,r11,r10
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stvx v5,r11,r9
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addi r11,r11,64
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stvx v6,r12,r10
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stvx v7,r12,r9
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addi r12,r12,64
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stvx v8,r11,r10
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stvx v9,r11,r9
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addi r11,r11,64
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stvx v10,r12,r10
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stvx v11,r12,r9
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mfspr r0,VRSAVE
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stvx v12,r11,r10
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stvx v13,r11,r9
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L(saveFP):
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stw r0,VR_VRSAVE(r1)
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/* Save floating registers. */
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/* Save floating registers. */
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stfd fp1,112(r1)
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stfd fp1,FPR_PARMS+0(r1)
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stfd fp2,120(r1)
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stfd fp2,FPR_PARMS+8(r1)
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stfd fp3,128(r1)
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stfd fp3,FPR_PARMS+16(r1)
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stfd fp4,136(r1)
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stfd fp4,FPR_PARMS+24(r1)
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stfd fp5,144(r1)
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stfd fp5,FPR_PARMS+32(r1)
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stfd fp6,152(r1)
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stfd fp6,FPR_PARMS+40(r1)
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stfd fp7,160(r1)
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stfd fp7,FPR_PARMS+48(r1)
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stfd fp8,168(r1)
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stfd fp8,FPR_PARMS+56(r1)
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stfd fp9,176(r1)
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stfd fp9,FPR_PARMS+64(r1)
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stfd fp10,184(r1)
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stfd fp10,FPR_PARMS+72(r1)
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stfd fp11,192(r1)
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stfd fp11,FPR_PARMS+80(r1)
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stfd fp12,200(r1)
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stfd fp13,208(r1)
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/* XXX TODO: store vmx registers. */
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/* Load the extra parameters. */
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addi r6,r1,48
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addi r7,r1,432
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li r0,-1
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li r0,-1
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stdu r0,0(r7)
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stfd fp12,FPR_PARMS+88(r1)
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stfd fp13,FPR_PARMS+96(r1)
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/* Load the extra parameters. */
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addi r6,r1,INT_PARMS
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addi r7,r1,STACK_FRAME
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/* Save link_map* and reloc_addr parms for later. */
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mr r31,r3
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mr r30,r4
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std r0,0(r7)
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bl JUMPTARGET(_dl_profile_fixup)
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bl JUMPTARGET(_dl_profile_fixup)
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nop
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/* Test *framesizep > 0 to see if need to do pltexit processing. */
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ld r0,STACK_FRAME(r1)
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/* Put the registers back. */
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/* Put the registers back. */
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ld r0,448+16(r1)
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lwz r12,VR_VRSAVE(r1)
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ld r10,104(r1)
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cmpdi cr1,r0,0
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ld r9,96(r1)
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cmpdi cr0,r12,0
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ld r8,88(r1)
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bgt cr1,L(do_pltexit)
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ld r7,80(r1)
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la r10,(VR_PARMS+0)(r1)
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la r9,(VR_PARMS+16)(r1)
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/* VRSAVE must be non-zero if VMX is present and VRs are in use. */
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beq L(restoreFXR)
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li r11,32
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li r12,64
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lvx v2,0,r10
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lvx v3,0,r9
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lvx v4,r11,r10
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lvx v5,r11,r9
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addi r11,r11,64
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lvx v6,r12,r10
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lvx v7,r12,r9
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addi r12,r12,64
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lvx v8,r11,r10
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lvx v9,r11,r9
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addi r11,r11,64
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lvx v10,r12,r10
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lvx v11,r12,r9
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lvx v12,r11,r10
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lvx v13,r11,r9
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L(restoreFXR):
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ld r0,FRAME_SIZE+16(r1)
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ld r10,INT_PARMS+56(r1)
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ld r9,INT_PARMS+48(r1)
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ld r8,INT_PARMS+40(r1)
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ld r7,INT_PARMS+32(r1)
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mtlr r0
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mtlr r0
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ld r0,8(r1)
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ld r0,8(r1)
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ld r6,72(r1)
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ld r6,INT_PARMS+24(r1)
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ld r5,64(r1)
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ld r5,INT_PARMS+16(r1)
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ld r4,56(r1)
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ld r4,INT_PARMS+8(r1)
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mtcrf 0xFF,r0
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mtcrf 0xFF,r0
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/* Load the target address, toc and static chain reg from the function
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/* Load the target address, toc and static chain reg from the function
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descriptor returned by fixup. */
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descriptor returned by fixup. */
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ld r0,0(r3)
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ld r0,0(r3)
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ld r2,8(r3)
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ld r2,8(r3)
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mtctr r0
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ld r11,16(r3)
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ld r11,16(r3)
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ld r3,48(r1)
|
ld r3,INT_PARMS+0(r1)
|
||||||
|
mtctr r0
|
||||||
/* Load the floating point registers. */
|
/* Load the floating point registers. */
|
||||||
lfd fp1,112(r1)
|
lfd fp1,FPR_PARMS+0(r1)
|
||||||
lfd fp2,120(r1)
|
lfd fp2,FPR_PARMS+8(r1)
|
||||||
lfd fp3,128(r1)
|
lfd fp3,FPR_PARMS+16(r1)
|
||||||
lfd fp4,136(r1)
|
lfd fp4,FPR_PARMS+24(r1)
|
||||||
lfd fp5,144(r1)
|
lfd fp5,FPR_PARMS+32(r1)
|
||||||
lfd fp6,152(r1)
|
lfd fp6,FPR_PARMS+40(r1)
|
||||||
lfd fp7,160(r1)
|
lfd fp7,FPR_PARMS+48(r1)
|
||||||
lfd fp8,168(r1)
|
lfd fp8,FPR_PARMS+56(r1)
|
||||||
lfd fp9,176(r1)
|
lfd fp9,FPR_PARMS+64(r1)
|
||||||
lfd fp10,184(r1)
|
lfd fp10,FPR_PARMS+72(r1)
|
||||||
lfd fp11,192(r1)
|
lfd fp11,FPR_PARMS+80(r1)
|
||||||
lfd fp12,200(r1)
|
lfd fp12,FPR_PARMS+88(r1)
|
||||||
lfd fp13,208(r1)
|
lfd fp13,FPR_PARMS+96(r1)
|
||||||
/* Unwind the stack frame, and jump. */
|
/* Unwind the stack frame, and jump. */
|
||||||
addi r1,r1,448
|
ld r31,584(r1)
|
||||||
|
ld r30,576(r1)
|
||||||
|
addi r1,r1,FRAME_SIZE
|
||||||
bctr
|
bctr
|
||||||
|
L(do_pltexit):
|
||||||
|
la r10,(VR_PARMS+0)(r1)
|
||||||
|
la r9,(VR_PARMS+16)(r1)
|
||||||
|
beq L(restoreFXR2)
|
||||||
|
li r11,32
|
||||||
|
li r12,64
|
||||||
|
lvx v2,0,r10
|
||||||
|
lvx v3,0,r9
|
||||||
|
|
||||||
|
lvx v4,r11,r10
|
||||||
|
lvx v5,r11,r9
|
||||||
|
addi r11,r11,64
|
||||||
|
|
||||||
|
lvx v6,r12,r10
|
||||||
|
lvx v7,r12,r9
|
||||||
|
addi r12,r12,64
|
||||||
|
|
||||||
|
lvx v8,r11,r10
|
||||||
|
lvx v9,r11,r9
|
||||||
|
addi r11,r11,64
|
||||||
|
|
||||||
|
lvx v10,r12,r10
|
||||||
|
lvx v11,r12,r9
|
||||||
|
|
||||||
|
lvx v12,r11,r10
|
||||||
|
lvx v13,r11,r9
|
||||||
|
L(restoreFXR2):
|
||||||
|
ld r0,FRAME_SIZE+16(r1)
|
||||||
|
ld r10,INT_PARMS+56(r1)
|
||||||
|
ld r9,INT_PARMS+48(r1)
|
||||||
|
ld r8,INT_PARMS+40(r1)
|
||||||
|
ld r7,INT_PARMS+32(r1)
|
||||||
|
mtlr r0
|
||||||
|
ld r0,8(r1)
|
||||||
|
ld r6,INT_PARMS+24(r1)
|
||||||
|
ld r5,INT_PARMS+16(r1)
|
||||||
|
ld r4,INT_PARMS+8(r1)
|
||||||
|
mtcrf 0xFF,r0
|
||||||
|
/* Load the target address, toc and static chain reg from the function
|
||||||
|
descriptor returned by fixup. */
|
||||||
|
ld r0,0(r3)
|
||||||
|
std r2,40(r1)
|
||||||
|
ld r2,8(r3)
|
||||||
|
ld r11,16(r3)
|
||||||
|
ld r3,INT_PARMS+0(r1)
|
||||||
|
mtctr r0
|
||||||
|
/* Load the floating point registers. */
|
||||||
|
lfd fp1,FPR_PARMS+0(r1)
|
||||||
|
lfd fp2,FPR_PARMS+8(r1)
|
||||||
|
lfd fp3,FPR_PARMS+16(r1)
|
||||||
|
lfd fp4,FPR_PARMS+24(r1)
|
||||||
|
lfd fp5,FPR_PARMS+32(r1)
|
||||||
|
lfd fp6,FPR_PARMS+40(r1)
|
||||||
|
lfd fp7,FPR_PARMS+48(r1)
|
||||||
|
lfd fp8,FPR_PARMS+56(r1)
|
||||||
|
lfd fp9,FPR_PARMS+64(r1)
|
||||||
|
lfd fp10,FPR_PARMS+72(r1)
|
||||||
|
lfd fp11,FPR_PARMS+80(r1)
|
||||||
|
lfd fp12,FPR_PARMS+88(r1)
|
||||||
|
lfd fp13,FPR_PARMS+96(r1)
|
||||||
|
/* Call the target function. */
|
||||||
|
bctrl
|
||||||
|
ld r2,40(r1)
|
||||||
|
lwz r12,VR_VRSAVE(r1)
|
||||||
|
/* But return here and store the return values. */
|
||||||
|
std r3,INT_RTN(r1)
|
||||||
|
std r4,INT_RTN+8(r1)
|
||||||
|
stfd fp1,FPR_PARMS+0(r1)
|
||||||
|
stfd fp2,FPR_PARMS+8(r1)
|
||||||
|
cmpdi cr0,r12,0
|
||||||
|
la r10,VR_RTN(r1)
|
||||||
|
stfd fp3,FPR_PARMS+16(r1)
|
||||||
|
stfd fp4,FPR_PARMS+24(r1)
|
||||||
|
mr r3,r31
|
||||||
|
mr r4,r30
|
||||||
|
beq L(callpltexit)
|
||||||
|
stvx v2,0,r10
|
||||||
|
L(callpltexit):
|
||||||
|
addi r5,r1,INT_PARMS
|
||||||
|
addi r6,r1,INT_RTN
|
||||||
|
bl JUMPTARGET(_dl_call_pltexit)
|
||||||
|
nop
|
||||||
|
/* Restore the return values from target function. */
|
||||||
|
lwz r12,VR_VRSAVE(r1)
|
||||||
|
ld r3,INT_RTN(r1)
|
||||||
|
ld r4,INT_RTN+8(r1)
|
||||||
|
lfd fp1,FPR_PARMS+0(r1)
|
||||||
|
lfd fp2,FPR_PARMS+8(r1)
|
||||||
|
cmpdi cr0,r12,0
|
||||||
|
la r10,VR_RTN(r1)
|
||||||
|
lfd fp3,FPR_PARMS+16(r1)
|
||||||
|
lfd fp4,FPR_PARMS+24(r1)
|
||||||
|
beq L(pltexitreturn)
|
||||||
|
lvx v2,0,r10
|
||||||
|
L(pltexitreturn):
|
||||||
|
ld r0,FRAME_SIZE+16(r1)
|
||||||
|
ld r31,584(r1)
|
||||||
|
ld r30,576(r1)
|
||||||
|
mtlr r0
|
||||||
|
ld r1,0(r1)
|
||||||
|
blr
|
||||||
END(_dl_profile_resolve)
|
END(_dl_profile_resolve)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user