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Check if SSE is available with HAS_CPU_FEATURE

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Similar to other CPU feature checks, check if SSE is available with
HAS_CPU_FEATURE.

	* sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use
	HAS_CPU_FEATURE to check for SSE.
	* sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
	* sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise.
	* sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise.
	* sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise.
	* sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise.
	* sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise.
	* sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise.
	* sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise.
	* sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise.
	* sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise.
	* sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise.
	* sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise.
	* sysdeps/i386/setfpucw.c (__setfpucw): Likewise.
	* sysdeps/x86/cpu-features.h (bit_cpu_SSE): New.
	(index_cpu_SSE): Likewise.
	(reg_SSE): Likewise.
This commit is contained in:
H.J. Lu 2017-04-07 07:44:40 -07:00
parent 893ba3eac9
commit bf7730194f
16 changed files with 39 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
ChangeLog
View File

@ -1,3 +1,24 @@
2017-04-07 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use
HAS_CPU_FEATURE to check for SSE.
* sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
* sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise.
* sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise.
* sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise.
* sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise.
* sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise.
* sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise.
* sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise.
* sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise.
* sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise.
* sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise.
* sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise.
* sysdeps/i386/setfpucw.c (__setfpucw): Likewise.
* sysdeps/x86/cpu-features.h (bit_cpu_SSE): New.
(index_cpu_SSE): Likewise.
(reg_SSE): Likewise.
2017-04-07 Paul Eggert <eggert@cs.ucla.edu>
* posix/getopt1.c: Include <config.h>, not "config.h".

2
sysdeps/i386/fpu/fclrexcpt.c
View File

@ -41,7 +41,7 @@ __feclearexcept (int excepts)
__asm__ ("fldenv %0" : : "m" (*&temp));
/* If the CPU supports SSE, we clear the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;

2
sysdeps/i386/fpu/fedisblxcpt.c
View File

@ -38,7 +38,7 @@ fedisableexcept (int excepts)
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;

2
sysdeps/i386/fpu/feenablxcpt.c
View File

@ -38,7 +38,7 @@ feenableexcept (int excepts)
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;

2
sysdeps/i386/fpu/fegetenv.c
View File

@ -31,7 +31,7 @@ __fegetenv (fenv_t *envp)
would block all exceptions. */
__asm__ ("fldenv %0" : : "m" (*envp));
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (envp->__eip));
/* Success. */

2
sysdeps/i386/fpu/fegetmode.c
View File

@ -26,7 +26,7 @@ int
fegetmode (femode_t *modep)
{
_FPU_GETCW (modep->__control_word);
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (modep->__mxcsr));
return 0;
}

2
sysdeps/i386/fpu/feholdexcpt.c
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@ -30,7 +30,7 @@ __feholdexcept (fenv_t *envp)
__asm__ volatile ("fnstenv %0; fnclex" : "=m" (*envp));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xwork;

2
sysdeps/i386/fpu/fesetenv.c
View File

@ -79,7 +79,7 @@ __fesetenv (const fenv_t *envp)
__asm__ ("fldenv %0" : : "m" (temp));
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int mxcsr;
__asm__ ("stmxcsr %0" : "=m" (mxcsr));

2
sysdeps/i386/fpu/fesetmode.c
View File

@ -35,7 +35,7 @@ fesetmode (const femode_t *modep)
else
cw = modep->__control_word;
_FPU_SETCW (cw);
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int mxcsr;
__asm__ ("stmxcsr %0" : "=m" (mxcsr));

2
sysdeps/i386/fpu/fesetround.c
View File

@ -37,7 +37,7 @@ __fesetround (int round)
__asm__ ("fldcw %0" : : "m" (*&cw));
/* If the CPU supports SSE we set the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xcw;

2
sysdeps/i386/fpu/feupdateenv.c
View File

@ -32,7 +32,7 @@ __feupdateenv (const fenv_t *envp)
__asm__ ("fnstsw %0" : "=m" (*&temp));
/* If the CPU supports SSE we test the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
temp = (temp | xtemp) & FE_ALL_EXCEPT;

2
sysdeps/i386/fpu/fgetexcptflg.c
View File

@ -34,7 +34,7 @@ __fegetexceptflag (fexcept_t *flagp, int excepts)
*flagp = temp & excepts & FE_ALL_EXCEPT;
/* If the CPU supports SSE, we clear the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int sse_exc;

2
sysdeps/i386/fpu/fsetexcptflg.c
View File

@ -41,7 +41,7 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts)
__asm__ ("fldenv %0" : : "m" (*&temp));
/* If the CPU supports SSE, we set the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;

2
sysdeps/i386/fpu/ftestexcept.c
View File

@ -32,7 +32,7 @@ fetestexcept (int excepts)
__asm__ ("fnstsw %0" : "=a" (temp));
/* If the CPU supports SSE we test the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
return (temp | xtemp) & excepts & FE_ALL_EXCEPT;

2
sysdeps/i386/setfpucw.c
View File

@ -39,7 +39,7 @@ __setfpucw (fpu_control_t set)
__asm__ ("fldcw %0" : : "m" (*&cw));
/* If the CPU supports SSE, we set the MXCSR as well. */
if ((GLRO(dl_hwcap) & HWCAP_I386_XMM) != 0)
if (HAS_CPU_FEATURE (SSE))
{
unsigned int xnew_exc;

4
sysdeps/x86/cpu-features.h
View File

@ -45,6 +45,7 @@
/* COMMON_CPUID_INDEX_1. */
#define bit_cpu_CX8 (1 << 8)
#define bit_cpu_CMOV (1 << 15)
#define bit_cpu_SSE (1 << 25)
#define bit_cpu_SSE2 (1 << 26)
#define bit_cpu_SSSE3 (1 << 9)
#define bit_cpu_SSE4_1 (1 << 19)
@ -82,6 +83,7 @@
# define index_cpu_CX8 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_CMOV COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_SSE COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_SSE2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
# define index_cpu_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
# define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
@ -228,6 +230,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define index_cpu_CX8 COMMON_CPUID_INDEX_1
# define index_cpu_CMOV COMMON_CPUID_INDEX_1
# define index_cpu_SSE COMMON_CPUID_INDEX_1
# define index_cpu_SSE2 COMMON_CPUID_INDEX_1
# define index_cpu_SSSE3 COMMON_CPUID_INDEX_1
# define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1
@ -246,6 +249,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define reg_CX8 edx
# define reg_CMOV edx
# define reg_SSE edx
# define reg_SSE2 edx
# define reg_SSSE3 ecx
# define reg_SSE4_1 ecx