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cheri: Implement 128-bit atomics
Arm Morello requires 128-bit atomics.
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@ -62,6 +62,8 @@
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__atg1_result = pre##_32_##post (mem, __VA_ARGS__); \
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else if (sizeof (*mem) == 8) \
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__atg1_result = pre##_64_##post (mem, __VA_ARGS__); \
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else if (sizeof (*mem) == 16) \
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__atg1_result = pre##_128_##post (mem, __VA_ARGS__); \
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else \
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abort (); \
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__atg1_result; \
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@ -77,6 +79,8 @@
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__atg2_result = pre##_32_##post (mem, __VA_ARGS__); \
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else if (sizeof (*mem) == 8) \
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__atg2_result = pre##_64_##post (mem, __VA_ARGS__); \
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else if (sizeof (*mem) == 16) \
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__atg2_result = pre##_128_##post (mem, __VA_ARGS__); \
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else \
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abort (); \
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__atg2_result; \
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@ -540,7 +544,11 @@
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/* We require 32b atomic operations; some archs also support 64b atomic
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operations. */
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void __atomic_link_error (void);
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# if __HAVE_64B_ATOMICS == 1
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# if defined __CHERI_PURE_CAPABILITY__
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# define __atomic_check_size(mem) \
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if ((sizeof (*mem) != 4) && (sizeof (*mem) != 8) && (sizeof (*mem) != 16)) \
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__atomic_link_error ();
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# elif __HAVE_64B_ATOMICS == 1
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# define __atomic_check_size(mem) \
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if ((sizeof (*mem) != 4) && (sizeof (*mem) != 8)) \
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__atomic_link_error ();
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@ -553,7 +561,12 @@ void __atomic_link_error (void);
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need other atomic operations of such sizes, and restricting the support to
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loads and stores makes this easier for archs that do not have native
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support for atomic operations to less-than-word-sized data. */
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# if __HAVE_64B_ATOMICS == 1
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# if defined __CHERI_PURE_CAPABILITY__
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# define __atomic_check_size_ls(mem) \
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if ((sizeof (*mem) != 1) && (sizeof (*mem) != 2) && (sizeof (*mem) != 4) \
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&& (sizeof (*mem) != 8) && (sizeof (*mem) != 16)) \
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__atomic_link_error ();
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# elif __HAVE_64B_ATOMICS == 1
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# define __atomic_check_size_ls(mem) \
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if ((sizeof (*mem) != 1) && (sizeof (*mem) != 2) && (sizeof (*mem) != 4) \
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&& (sizeof (*mem) != 8)) \
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@ -54,6 +54,13 @@
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model, __ATOMIC_RELAXED); \
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})
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# define __arch_compare_and_exchange_bool_128_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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!__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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})
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# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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@ -86,6 +93,14 @@
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__oldval; \
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})
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# define __arch_compare_and_exchange_val_128_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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__oldval; \
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})
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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@ -118,6 +133,9 @@
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# define __arch_exchange_64_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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# define __arch_exchange_128_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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# define atomic_exchange_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
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@ -139,6 +157,9 @@
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# define __arch_exchange_and_add_64_int(mem, value, model) \
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__atomic_fetch_add (mem, value, model)
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# define __arch_exchange_and_add_128_int(mem, value, model) \
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__atomic_fetch_add (mem, value, model)
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# define atomic_exchange_and_add_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
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__ATOMIC_ACQUIRE)
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