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AArch64: Optimize memset
Improve small memsets by avoiding branches and use overlapping stores. Use DC ZVA for copies over 128 bytes. Remove unnecessary code for ZVA sizes other than 64 and 128. Performance of random memset benchmark improves by 24% on Neoverse N1. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
This commit is contained in:
Wilco Dijkstra
parent
3fc1d3bc33
commit
cec3aef324
@ -1,4 +1,5 @@
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/* Copyright (C) 2012-2024 Free Software Foundation, Inc.
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/* Generic optimized memset using SIMD.
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Copyright (C) 2012-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@ -17,7 +18,6 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include "memset-reg.h"
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#ifndef MEMSET
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# define MEMSET memset
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@ -25,130 +25,132 @@
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses
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* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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*
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*/
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ENTRY (MEMSET)
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define zva_val x5
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#define off x3
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#define dstend2 x5
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ENTRY (MEMSET)
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PTR_ARG (0)
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SIZE_ARG (2)
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dup v0.16B, valw
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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mov val, v0.D[0]
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b.lo L(set_small)
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add dstend, dstin, count
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cmp count, 64
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b.hs L(set_128)
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/* Set 16..63 bytes. */
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mov off, 16
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and off, off, count, lsr 1
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sub dstend2, dstend, off
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str q0, [dstin]
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str q0, [dstin, off]
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str q0, [dstend2, -16]
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str q0, [dstend, -16]
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ret
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.p2align 4
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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nop
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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L(set_small):
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add dstend, dstin, count
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cmp count, 4
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b.lo 2f
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lsr off, count, 3
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sub dstend2, dstend, off, lsl 2
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str s0, [dstin]
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str s0, [dstin, off, lsl 2]
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str s0, [dstend2, -4]
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str s0, [dstend, -4]
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ret
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/* Set 0..3 bytes. */
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2: cbz count, 3f
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lsr off, count, 1
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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strb valw, [dstin, off]
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strb valw, [dstend, -1]
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3: ret
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/* Set 17..96 bytes. */
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L(set_medium):
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str q0, [dstin]
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tbnz count, 6, L(set96)
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str q0, [dstend, -16]
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tbz count, 5, 1f
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str q0, [dstin, 16]
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str q0, [dstend, -32]
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1: ret
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.p2align 4
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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str q0, [dstin, 16]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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nop
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L(set_long):
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and valw, valw, 255
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L(set_128):
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bic dst, dstin, 15
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str q0, [dstin]
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cmp count, 256
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ccmp valw, 0, 0, cs
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b.eq L(try_zva)
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L(no_zva):
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sub count, dstend, dst /* Count is 16 too large. */
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sub dst, dst, 16 /* Dst is biased by -32. */
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sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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1: stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]!
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L(tail64):
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subs count, count, 64
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b.hi 1b
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2: stp q0, q0, [dstend, -64]
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cmp count, 128
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b.hi L(set_long)
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stp q0, q0, [dstin]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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L(try_zva):
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#ifndef ZVA64_ONLY
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.p2align 3
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mrs tmp1, dczid_el0
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tbnz tmp1w, 4, L(no_zva)
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and tmp1w, tmp1w, 15
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cmp tmp1w, 4 /* ZVA size is 64 bytes. */
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b.ne L(zva_128)
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nop
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#endif
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/* Write the first and last 64 byte aligned block using stp rather
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than using DC ZVA. This is faster on some cores.
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*/
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.p2align 4
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L(zva_64):
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L(set_long):
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str q0, [dstin]
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str q0, [dst, 16]
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tst valw, 255
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b.ne L(no_zva)
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#ifndef ZVA64_ONLY
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mrs zva_val, dczid_el0
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and zva_val, zva_val, 31
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cmp zva_val, 4 /* ZVA size is 64 bytes. */
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b.ne L(zva_128)
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#endif
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stp q0, q0, [dst, 32]
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bic dst, dstin, 63
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sub count, dstend, dst /* Count is now 64 too large. */
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sub count, count, 64 + 64 /* Adjust count and bias for loop. */
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/* Write last bytes before ZVA loop. */
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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.p2align 4
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L(zva64_loop):
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add dst, dst, 64
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dc zva, dst
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subs count, count, 64
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b.hi L(zva64_loop)
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ret
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.p2align 3
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L(no_zva):
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sub count, dstend, dst /* Count is 32 too large. */
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sub count, count, 64 + 32 /* Adjust count and bias for loop. */
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L(no_zva_loop):
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stp q0, q0, [dst, 32]
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bic dst, dst, 63
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stp q0, q0, [dst, 64]
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stp q0, q0, [dst, 96]
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sub count, dstend, dst /* Count is now 128 too large. */
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sub count, count, 128+64+64 /* Adjust count and bias for loop. */
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add dst, dst, 128
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1: dc zva, dst
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add dst, dst, 64
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subs count, count, 64
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b.hi 1b
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stp q0, q0, [dst, 0]
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stp q0, q0, [dst, 32]
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b.hi L(no_zva_loop)
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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#ifndef ZVA64_ONLY
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.p2align 3
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.p2align 4
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L(zva_128):
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cmp tmp1w, 5 /* ZVA size is 128 bytes. */
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b.ne L(zva_other)
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cmp zva_val, 5 /* ZVA size is 128 bytes. */
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b.ne L(no_zva)
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]
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stp q0, q0, [dst, 96]
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bic dst, dst, 127
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sub count, dstend, dst /* Count is now 128 too large. */
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sub count, count, 128+128 /* Adjust count and bias for loop. */
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add dst, dst, 128
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1: dc zva, dst
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add dst, dst, 128
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sub count, count, 128 + 128 /* Adjust count and bias for loop. */
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1: add dst, dst, 128
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dc zva, dst
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subs count, count, 128
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b.hi 1b
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stp q0, q0, [dstend, -128]
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@ -156,35 +158,6 @@ L(zva_128):
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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L(zva_other):
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mov tmp2w, 4
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lsl zva_lenw, tmp2w, tmp1w
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add tmp1, zva_len, 64 /* Max alignment bytes written. */
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cmp count, tmp1
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blo L(no_zva)
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sub tmp2, zva_len, 1
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add tmp1, dst, zva_len
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add dst, dst, 16
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subs count, tmp1, dst /* Actual alignment bytes to write. */
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bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */
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beq 2f
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1: stp q0, q0, [dst], 64
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stp q0, q0, [dst, -32]
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subs count, count, 64
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b.hi 1b
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2: mov dst, tmp1
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sub count, dstend, tmp1 /* Remaining bytes to write. */
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subs count, count, zva_len
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b.lo 4f
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3: dc zva, dst
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add dst, dst, zva_len
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subs count, count, zva_len
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b.hs 3b
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4: add count, count, zva_len
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sub dst, dst, 32 /* Bias dst for tail loop. */
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b L(tail64)
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#endif
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END (MEMSET)
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