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Restore non-v9 32-bit sparc build.
* sysdeps/sparc/sparc32/bits/atomic.h: Include sysdep.h to get HWCAP_* values only after the memory barriers have been defined. (atomic_full_barrier): Define. (atomic_read_barrier): Define. (atomic_write_barrier): Define.
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@ -1,3 +1,11 @@
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2012-04-25 David S. Miller <davem@davemloft.net>
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* sysdeps/sparc/sparc32/bits/atomic.h: Include sysdep.h to get
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HWCAP_* values only after the memory barriers have been defined.
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(atomic_full_barrier): Define.
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(atomic_read_barrier): Define.
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(atomic_write_barrier): Define.
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2012-04-26 Siddhesh Poyarekar <siddhesh@redhat.com>
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* shlib-versions: Add libgcc_s version information.
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@ -21,7 +21,6 @@
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#define _BITS_ATOMIC_H 1
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#include <stdint.h>
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#include <sysdep.h>
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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@ -231,6 +230,10 @@ volatile unsigned char __sparc32_atomic_locks[64]
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abort (); \
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__v7_exchange_24_rel (mem, newval); })
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# define atomic_full_barrier() __asm ("" ::: "memory")
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# define atomic_read_barrier() atomic_full_barrier ()
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# define atomic_write_barrier() atomic_full_barrier ()
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#else
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/* In libc.a/libpthread.a etc. we don't know if we'll be run on
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@ -319,6 +322,35 @@ extern uint64_t _dl_hwcap __attribute__((weak));
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__acev_w24ret = __v7_exchange_24_rel (mem, newval); \
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__acev_w24ret; })
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#define atomic_full_barrier() \
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do { \
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if (__atomic_is_v9) \
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/* membar #LoadLoad | #LoadStore | #StoreLoad | #StoreStore */ \
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__asm __volatile (".word 0x8143e00f" : : : "memory"); \
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else \
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__asm __volatile ("" : : : "memory"); \
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} while (0)
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#define atomic_read_barrier() \
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do { \
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if (__atomic_is_v9) \
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/* membar #LoadLoad | #LoadStore */ \
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__asm __volatile (".word 0x8143e005" : : : "memory"); \
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else \
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__asm __volatile ("" : : : "memory"); \
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} while (0)
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#define atomic_write_barrier() \
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do { \
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if (__atomic_is_v9) \
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/* membar #StoreLoad | #StoreStore */ \
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__asm __volatile (".word 0x8143e00a" : : : "memory"); \
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else \
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__asm __volatile ("" : : : "memory"); \
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} while (0)
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#endif
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#include <sysdep.h>
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#endif /* bits/atomic.h */
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