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Fix whitespace issues.
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parent
057edf90e0
commit
d6ac9329b3
@ -43,16 +43,16 @@
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.align 7
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EALIGN (BP_SYM (memcpy), 5, 0)
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CALL_MCOUNT
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CALL_MCOUNT
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dcbt 0,r4 /* Prefetch ONE SRC cacheline */
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cmplwi cr1,r5,16 /* is size < 16 ? */
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mr r6,r3
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mr r6,r3
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blt+ cr1,.Lshortcopy
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.Lbigcopy:
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neg r8,r3 /* LS 3 bits = # bytes to 8-byte dest bdry */
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clrlwi r8,r8,32-4 /* aling to 16byte boundary */
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clrlwi r8,r8,32-4 /* aling to 16byte boundary */
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sub r7,r4,r3
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cmplwi cr0,r8,0
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beq+ .Ldst_aligned
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@ -112,8 +112,8 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.LprefetchSRC:
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dcbt r12,r4
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addi r12,r12,128
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bdnz .LprefetchSRC
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addi r12,r12,128
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bdnz .LprefetchSRC
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.Lnocacheprefetch:
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mtctr r7
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@ -122,7 +122,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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beq cr6,.Lcachelinealigned
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.Laligntocacheline:
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lfd fp9,0x08(r4)
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lfd fp9,0x08(r4)
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lfdu fp10,0x10(r4)
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stfd fp9,0x08(r6)
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stfdu fp10,0x10(r6)
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@ -131,10 +131,10 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.Lcachelinealigned: /* copy while cache lines */
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blt- cr1,.Llessthancacheline /* size <128 */
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blt- cr1,.Llessthancacheline /* size <128 */
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.Louterloop:
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cmpwi r11,0
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cmpwi r11,0
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mtctr r11
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beq- .Lendloop
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@ -142,7 +142,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.align 4
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/* Copy whole cachelines, optimized by prefetching SRC cacheline */
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.Lloop: /* Copy aligned body */
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.Lloop: /* Copy aligned body */
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dcbt r12,r4 /* PREFETCH SOURCE some cache lines ahead */
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lfd fp9, 0x08(r4)
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dcbz r11,r6
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@ -186,7 +186,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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beq- .Lendloop2
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mtctr r10
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.Lloop2: /* Copy aligned body */
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.Lloop2: /* Copy aligned body */
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lfd fp9, 0x08(r4)
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lfd fp10, 0x10(r4)
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lfd fp11, 0x18(r4)
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@ -206,7 +206,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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mtctr r7
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.Lcopy_remaining:
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lfd fp9,0x08(r4)
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lfd fp9,0x08(r4)
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lfdu fp10,0x10(r4)
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stfd fp9,0x08(r6)
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stfdu fp10,0x10(r6)
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@ -214,7 +214,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.Ldo_lt16: /* less than 16 ? */
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cmplwi cr0,r5,0 /* copy remaining bytes (0-15) */
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beqlr+ /* no rest to copy */
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beqlr+ /* no rest to copy */
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addi r4,r4,8
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addi r6,r6,8
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@ -43,16 +43,16 @@
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.align 7
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EALIGN (BP_SYM (memcpy), 5, 0)
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CALL_MCOUNT 3
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CALL_MCOUNT 3
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dcbt 0,r4 /* Prefetch ONE SRC cacheline */
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cmpldi cr1,r5,16 /* is size < 16 ? */
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mr r6,r3
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mr r6,r3
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blt+ cr1,.Lshortcopy
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.Lbigcopy:
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neg r8,r3 /* LS 3 bits = # bytes to 8-byte dest bdry */
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clrldi r8,r8,64-4 /* aling to 16byte boundary */
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clrldi r8,r8,64-4 /* aling to 16byte boundary */
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sub r7,r4,r3
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cmpldi cr0,r8,0
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beq+ .Ldst_aligned
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@ -112,8 +112,8 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.LprefetchSRC:
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dcbt r12,r4
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addi r12,r12,128
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bdnz .LprefetchSRC
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addi r12,r12,128
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bdnz .LprefetchSRC
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.Lnocacheprefetch:
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mtctr r7
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@ -122,7 +122,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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beq cr6,.Lcachelinealigned
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.Laligntocacheline:
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ld r9,0x08(r4)
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ld r9,0x08(r4)
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ldu r7,0x10(r4)
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std r9,0x08(r6)
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stdu r7,0x10(r6)
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@ -131,10 +131,10 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.Lcachelinealigned: /* copy while cache lines */
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blt- cr1,.Llessthancacheline /* size <128 */
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blt- cr1,.Llessthancacheline /* size <128 */
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.Louterloop:
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cmpdi r11,0
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cmpdi r11,0
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mtctr r11
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beq- .Lendloop
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@ -142,7 +142,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.align 4
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/* Copy whole cachelines, optimized by prefetching SRC cacheline */
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.Lloop: /* Copy aligned body */
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.Lloop: /* Copy aligned body */
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dcbt r12,r4 /* PREFETCH SOURCE some cache lines ahead */
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ld r9, 0x08(r4)
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dcbz r11,r6
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@ -186,7 +186,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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beq- .Lendloop2
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mtctr r10
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.Lloop2: /* Copy aligned body */
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.Lloop2: /* Copy aligned body */
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ld r9, 0x08(r4)
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ld r7, 0x10(r4)
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ld r8, 0x18(r4)
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@ -206,7 +206,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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mtctr r7
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.Lcopy_remaining:
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ld r8,0x08(r4)
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ld r8,0x08(r4)
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ldu r7,0x10(r4)
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std r8,0x08(r6)
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stdu r7,0x10(r6)
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@ -214,7 +214,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
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.Ldo_lt16: /* less than 16 ? */
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cmpldi cr0,r5,0 /* copy remaining bytes (0-15) */
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beqlr+ /* no rest to copy */
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beqlr+ /* no rest to copy */
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addi r4,r4,8
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addi r6,r6,8
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