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2013-01-08 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/memcpy.S: Change prefetch hint, reorder partial loads and stores, set and use MAX_PREFETCH_SIZE.
This commit is contained in:
parent
eede9df980
commit
d9014c080a
@ -1,3 +1,8 @@
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2013-01-08 Steve Ellcey <sellcey@mips.com>
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* sysdeps/mips/memcpy.S: Change prefetch hint, reorder partial
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loads and stores, set and use MAX_PREFETCH_SIZE.
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2013-01-08 Andreas Jaeger <aj@suse.de>
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[BZ# 14985]
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@ -26,12 +26,12 @@
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#include <regdef.h>
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#include <sys/asm.h>
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#define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
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#elif _COMPILING_NEWLIB
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#include "machine/asm.h"
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#include "machine/regdef.h"
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#define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
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#define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
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#else
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#include <regdef.h>
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#include <sys/asm.h>
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@ -44,7 +44,7 @@
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#endif
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#endif
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#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
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#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32))
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#ifndef DISABLE_DOUBLE
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#define USE_DOUBLE
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#endif
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@ -138,14 +138,15 @@
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* get 64 bytes in that case. The assumption is that each individual
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* prefetch brings in 32 bytes.
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*/
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#ifdef USE_DOUBLE
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# define PREFETCH_CHUNK 64
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# define PREFETCH_FOR_LOAD(chunk, reg) \
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pref PREFETCH_LOAD_HINT, (chunk)*32(reg); \
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pref PREFETCH_LOAD_HINT, ((chunk)+1)*32(reg)
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pref PREFETCH_LOAD_HINT, (chunk)*64(reg); \
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pref PREFETCH_LOAD_HINT, ((chunk)*64)+32(reg)
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# define PREFETCH_FOR_STORE(chunk, reg) \
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pref PREFETCH_STORE_HINT, (chunk)*32(reg); \
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pref PREFETCH_STORE_HINT, ((chunk)+1)*32(reg)
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pref PREFETCH_STORE_HINT, (chunk)*64(reg); \
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pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg)
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#else
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# define PREFETCH_CHUNK 32
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# define PREFETCH_FOR_LOAD(chunk, reg) \
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@ -153,7 +154,28 @@
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# define PREFETCH_FOR_STORE(chunk, reg) \
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pref PREFETCH_STORE_HINT, (chunk)*32(reg)
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#endif
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# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK)
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/* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less
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* then PREFETCH_CHUNK, the assumed size of each prefetch. If the real size
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* of a prefetch is greater then MAX_PREFETCH_SIZE and the PREPAREFORSTORE
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* hint is used, the code will not work corrrectly. If PREPAREFORSTORE is not
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* used then MAX_PREFETCH_SIZE does not matter. */
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#define MAX_PREFETCH_SIZE 128
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/* PREFETCH_LIMIT is set based on the fact that we neve use an offset greater
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* then 5 on a STORE prefetch and that a single prefetch can never be larger
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* then MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because
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* we actually do two prefetches in that case, one 32 bytes after the other. */
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#ifdef USE_DOUBLE
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# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE
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#else
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# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE
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#endif
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#if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \
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&& ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE)
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/* We cannot handle this because the initial prefetches may fetch bytes that
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* are before the buffer being copied. We start copies with an offset
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* of 4 so avoid this situation when using PREPAREFORSTORE. */
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#error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small."
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#endif
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#else /* USE_PREFETCH not defined */
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# define PREFETCH_FOR_LOAD(offset, reg)
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# define PREFETCH_FOR_STORE(offset, reg)
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@ -169,7 +191,7 @@
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#define REG1 t1
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#define REG2 t2
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#define REG3 t3
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#if _MIPS_SIM == _ABIO32
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#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABIO64))
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# define REG4 t4
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# define REG5 t5
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# define REG6 t6
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@ -258,7 +280,11 @@ L(memcpy):
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*/
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slti t2,a2,(2 * NSIZE)
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bne t2,zero,L(lastb)
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#if defined(RETURN_FIRST_PREFETCH) || defined(RETURN_LAST_PREFETCH)
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move v0,zero
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#else
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move v0,a0
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#endif
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/*
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* If src and dst have different alignments, go to L(unaligned), if they
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* have the same alignment (but are not actually aligned) do a partial
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@ -306,22 +332,46 @@ L(aligned):
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PREFETCH_FOR_LOAD (0, a1)
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PREFETCH_FOR_LOAD (1, a1)
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PREFETCH_FOR_LOAD (2, a1)
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PREFETCH_FOR_STORE (1, a0)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
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bgtz v1,L(loop16w)
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nop
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#endif
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PREFETCH_FOR_STORE (2, a0)
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L(loop16w):
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PREFETCH_FOR_LOAD (3, a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
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PREFETCH_FOR_STORE (1, a0)
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PREFETCH_FOR_STORE (2, a0)
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PREFETCH_FOR_STORE (3, a0)
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#endif
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#if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH)
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#if PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE
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sltu v1,t9,a0
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bgtz v1,L(skip_set)
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nop
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
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L(skip_set):
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#else
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
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#endif
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#endif
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#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH) \
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&& (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*3)
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#ifdef USE_DOUBLE
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PTR_ADDIU v0,v0,32
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#endif
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#endif
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L(loop16w):
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C_LD t0,UNIT(0)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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bgtz v1,L(skip_pref30_96)
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sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
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bgtz v1,L(skip_pref)
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#endif
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C_LD t1,UNIT(1)(a1)
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PREFETCH_FOR_STORE (3, a0)
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L(skip_pref30_96):
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PREFETCH_FOR_STORE (4, a0)
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PREFETCH_FOR_STORE (5, a0)
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#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH)
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5)
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#ifdef USE_DOUBLE
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PTR_ADDIU v0,v0,32
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#endif
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#endif
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L(skip_pref):
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C_LD REG2,UNIT(2)(a1)
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C_LD REG3,UNIT(3)(a1)
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C_LD REG4,UNIT(4)(a1)
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@ -340,12 +390,7 @@ L(skip_pref30_96):
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C_ST REG7,UNIT(7)(a0)
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C_LD t0,UNIT(8)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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bgtz v1,L(skip_pref30_128)
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#endif
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C_LD t1,UNIT(9)(a1)
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PREFETCH_FOR_STORE (4, a0)
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L(skip_pref30_128):
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C_LD REG2,UNIT(10)(a1)
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C_LD REG3,UNIT(11)(a1)
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C_LD REG4,UNIT(12)(a1)
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@ -362,9 +407,6 @@ L(skip_pref30_128):
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C_ST REG6,UNIT(14)(a0)
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C_ST REG7,UNIT(15)(a0)
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PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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#endif
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bne a0,a3,L(loop16w)
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PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
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move a2,t8
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@ -416,8 +458,8 @@ L(chk1w):
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/* copying in words (4-byte or 8-byte chunks) */
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L(wordCopy_loop):
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C_LD REG3,UNIT(0)(a1)
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PTR_ADDIU a1,a1,UNIT(1)
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PTR_ADDIU a0,a0,UNIT(1)
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PTR_ADDIU a1,a1,UNIT(1)
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bne a0,a3,L(wordCopy_loop)
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C_ST REG3,UNIT(-1)(a0)
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@ -427,8 +469,8 @@ L(lastb):
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PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
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L(lastbloop):
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lb v1,0(a1)
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PTR_ADDIU a1,a1,1
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PTR_ADDIU a0,a0,1
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PTR_ADDIU a1,a1,1
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bne a0,a3,L(lastbloop)
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sb v1,-1(a0)
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L(leave):
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@ -475,35 +517,46 @@ L(ua_chk16w):
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PREFETCH_FOR_LOAD (0, a1)
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PREFETCH_FOR_LOAD (1, a1)
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PREFETCH_FOR_LOAD (2, a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
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PREFETCH_FOR_STORE (1, a0)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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bgtz v1,L(ua_loop16w) /* skip prefetch for too short arrays */
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nop
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#endif
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PREFETCH_FOR_STORE (2, a0)
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PREFETCH_FOR_STORE (3, a0)
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#endif
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#if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH)
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#if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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bgtz v1,L(ua_skip_set)
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nop
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4)
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L(ua_skip_set):
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#else
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PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1)
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#endif
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#endif
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L(ua_loop16w):
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PREFETCH_FOR_LOAD (3, a1)
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C_LDHI t0,UNIT(0)(a1)
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C_LDLO t0,UNITM1(1)(a1)
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C_LDHI t1,UNIT(1)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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bgtz v1,L(ua_skip_pref30_96)
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#endif
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C_LDLO t1,UNITM1(2)(a1)
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PREFETCH_FOR_STORE (3, a0)
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L(ua_skip_pref30_96):
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C_LDHI REG2,UNIT(2)(a1)
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C_LDLO REG2,UNITM1(3)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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bgtz v1,L(ua_skip_pref)
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#endif
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C_LDHI REG3,UNIT(3)(a1)
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C_LDLO REG3,UNITM1(4)(a1)
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PREFETCH_FOR_STORE (4, a0)
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PREFETCH_FOR_STORE (5, a0)
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L(ua_skip_pref):
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C_LDHI REG4,UNIT(4)(a1)
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C_LDLO REG4,UNITM1(5)(a1)
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C_LDHI REG5,UNIT(5)(a1)
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C_LDLO REG5,UNITM1(6)(a1)
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C_LDHI REG6,UNIT(6)(a1)
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C_LDLO REG6,UNITM1(7)(a1)
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C_LDHI REG7,UNIT(7)(a1)
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C_LDLO t0,UNITM1(1)(a1)
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C_LDLO t1,UNITM1(2)(a1)
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C_LDLO REG2,UNITM1(3)(a1)
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C_LDLO REG3,UNITM1(4)(a1)
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C_LDLO REG4,UNITM1(5)(a1)
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C_LDLO REG5,UNITM1(6)(a1)
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C_LDLO REG6,UNITM1(7)(a1)
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C_LDLO REG7,UNITM1(8)(a1)
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PREFETCH_FOR_LOAD (4, a1)
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C_ST t0,UNIT(0)(a0)
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@ -515,25 +568,20 @@ L(ua_skip_pref30_96):
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C_ST REG6,UNIT(6)(a0)
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C_ST REG7,UNIT(7)(a0)
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C_LDHI t0,UNIT(8)(a1)
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C_LDLO t0,UNITM1(9)(a1)
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C_LDHI t1,UNIT(9)(a1)
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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bgtz v1,L(ua_skip_pref30_128)
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#endif
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C_LDLO t1,UNITM1(10)(a1)
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PREFETCH_FOR_STORE (4, a0)
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L(ua_skip_pref30_128):
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C_LDHI REG2,UNIT(10)(a1)
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C_LDLO REG2,UNITM1(11)(a1)
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C_LDHI REG3,UNIT(11)(a1)
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C_LDLO REG3,UNITM1(12)(a1)
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C_LDHI REG4,UNIT(12)(a1)
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C_LDLO REG4,UNITM1(13)(a1)
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C_LDHI REG5,UNIT(13)(a1)
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C_LDLO REG5,UNITM1(14)(a1)
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C_LDHI REG6,UNIT(14)(a1)
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C_LDLO REG6,UNITM1(15)(a1)
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C_LDHI REG7,UNIT(15)(a1)
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C_LDLO t0,UNITM1(9)(a1)
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C_LDLO t1,UNITM1(10)(a1)
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C_LDLO REG2,UNITM1(11)(a1)
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C_LDLO REG3,UNITM1(12)(a1)
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C_LDLO REG4,UNITM1(13)(a1)
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C_LDLO REG5,UNITM1(14)(a1)
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C_LDLO REG6,UNITM1(15)(a1)
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C_LDLO REG7,UNITM1(16)(a1)
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PREFETCH_FOR_LOAD (5, a1)
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C_ST t0,UNIT(8)(a0)
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@ -545,9 +593,6 @@ L(ua_skip_pref30_128):
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C_ST REG6,UNIT(14)(a0)
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C_ST REG7,UNIT(15)(a0)
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PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
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#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0
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#endif
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bne a0,a3,L(ua_loop16w)
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PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
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move a2,t8
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@ -564,20 +609,20 @@ L(ua_chkw):
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beq a2,t8,L(ua_chk1w) /* When a2=t8, no 32-byte chunk */
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nop
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C_LDHI t0,UNIT(0)(a1)
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C_LDLO t0,UNITM1(1)(a1)
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C_LDHI t1,UNIT(1)(a1)
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C_LDLO t1,UNITM1(2)(a1)
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C_LDHI REG2,UNIT(2)(a1)
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C_LDLO REG2,UNITM1(3)(a1)
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C_LDHI REG3,UNIT(3)(a1)
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C_LDLO REG3,UNITM1(4)(a1)
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C_LDHI REG4,UNIT(4)(a1)
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C_LDLO REG4,UNITM1(5)(a1)
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C_LDHI REG5,UNIT(5)(a1)
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C_LDLO REG5,UNITM1(6)(a1)
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C_LDHI REG6,UNIT(6)(a1)
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C_LDLO REG6,UNITM1(7)(a1)
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C_LDHI REG7,UNIT(7)(a1)
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C_LDLO t0,UNITM1(1)(a1)
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C_LDLO t1,UNITM1(2)(a1)
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C_LDLO REG2,UNITM1(3)(a1)
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C_LDLO REG3,UNITM1(4)(a1)
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C_LDLO REG4,UNITM1(5)(a1)
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C_LDLO REG5,UNITM1(6)(a1)
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C_LDLO REG6,UNITM1(7)(a1)
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C_LDLO REG7,UNITM1(8)(a1)
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PTR_ADDIU a1,a1,UNIT(8)
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C_ST t0,UNIT(0)(a0)
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@ -603,8 +648,8 @@ L(ua_chk1w):
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L(ua_wordCopy_loop):
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C_LDHI v1,UNIT(0)(a1)
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C_LDLO v1,UNITM1(1)(a1)
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PTR_ADDIU a1,a1,UNIT(1)
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PTR_ADDIU a0,a0,UNIT(1)
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PTR_ADDIU a1,a1,UNIT(1)
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bne a0,a3,L(ua_wordCopy_loop)
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C_ST v1,UNIT(-1)(a0)
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@ -614,8 +659,8 @@ L(ua_smallCopy):
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PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
|
||||
L(ua_smallCopy_loop):
|
||||
lb v1,0(a1)
|
||||
PTR_ADDIU a1,a1,1
|
||||
PTR_ADDIU a0,a0,1
|
||||
PTR_ADDIU a1,a1,1
|
||||
bne a0,a3,L(ua_smallCopy_loop)
|
||||
sb v1,-1(a0)
|
||||
|
||||
@ -625,6 +670,8 @@ L(ua_smallCopy_loop):
|
||||
.set at
|
||||
.set reorder
|
||||
END(MEMCPY_NAME)
|
||||
#ifndef ANDROID_CHANGES
|
||||
#ifdef _LIBC
|
||||
libc_hidden_builtin_def (MEMCPY_NAME)
|
||||
#endif
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user