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[powerpc] fenv_private.h clean up

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fenv_private.h includes unused functions, magic macro constants, and
some replicated common code fragments.

Remove unused functions, replace magic constants with constants from
fenv_libc.h, and refactor replicated code.

Suggested-by: Paul E. Murphy <murphyp@linux.ibm.com>
Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
This commit is contained in:
Paul A. Clarke 2019-09-19 09:13:14 -05:00
parent 9a44050e74
commit e3d85df50b
9 changed files with 67 additions and 117 deletions
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29
ChangeLog
View File

@ -1,3 +1,32 @@
2019-09-27 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h:
(__TEST_AND_ENTER_NON_STOP): New.
(__TEST_AND_EXIT_NON_STOP): New.
* sysdeps/powerpc/fpu/fenv_private.h
(_FPU_ALL_TRAPS): Delete, replace with FPSCR_ENABLES_MASK.
(_FPU_MASK_RN): Delete.
(_FPU_MASK_NOT_RN_NI): Delete.
(_FPU_MASK_TRAPS_RN): Delete, replace with ~FPSCR_CONTROL_MASK.
(_FPU_MASK_FRAC_INEX_RET_CC): Delete, replace with ~FPSCR_STATUS_MASK.
(__libc_feholdbits_ppc): Delete, move code into
libc_feholdexcept_setround_ppc.
(libc_feholdexcept_ppc): Delete.
(libc_fesetround_ppc): Delete.
(libc_fetestexcept_ppc): Delete.
(libc_feholdsetround_ppc): Delete.
(__libc_femergeenv_ppc): Use __TEST_AND_ENTER/EXIT_NON_STOP.
(libc_feholdsetround_noex_ppc_ctx): Likewise.
(libc_feupdateenv_test_ppc): Use FPSCR defines.
* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Use
__TEST_AND_ENTER_NON_STOP.
* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
* sysdeps/powerpc/fpu/feholdexcpt.c (__feholdexcept): Likewise.
* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise.
* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
* sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Likewise.
(_FPU_MASK_ALL): Delete.
2019-09-27 Joseph Myers <joseph@codesourcery.com> 2019-09-27 Joseph Myers <joseph@codesourcery.com>
* sysdeps/gnu/netinet/tcp.h (TCP_TX_DELAY): New macro. * sysdeps/gnu/netinet/tcp.h (TCP_TX_DELAY): New macro.

3
sysdeps/powerpc/fpu/fedisblxcpt.c
View File

@ -43,8 +43,7 @@ fedisableexcept (int excepts)
if (fe.l != curr.l) if (fe.l != curr.l)
fesetenv_mode (fe.fenv); fesetenv_mode (fe.fenv);
if (new == 0 && result != 0) __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l);
(void)__fe_mask_env ();
return result; return result;
} }

3
sysdeps/powerpc/fpu/feenablxcpt.c
View File

@ -43,8 +43,7 @@ feenableexcept (int excepts)
if (fe.l != curr.l) if (fe.l != curr.l)
fesetenv_mode (fe.fenv); fesetenv_mode (fe.fenv);
if (new != 0 && result == 0) __TEST_AND_EXIT_NON_STOP (0ULL, fe.l);
(void) __fe_nomask_env_priv ();
return result; return result;
} }

7
sysdeps/powerpc/fpu/feholdexcpt.c
View File

@ -18,7 +18,6 @@
#include <fenv_libc.h> #include <fenv_libc.h>
#include <fpu_control.h> #include <fpu_control.h>
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
int int
__feholdexcept (fenv_t *envp) __feholdexcept (fenv_t *envp)
@ -35,11 +34,7 @@ __feholdexcept (fenv_t *envp)
if (new.l == old.l) if (new.l == old.l)
return 0; return 0;
/* If the old env had any enabled exceptions, then mask SIGFPE in the __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
MSR FE0/FE1 bits. This may allow the FPU to run faster because it
always takes the default action and can not generate SIGFPE. */
if ((old.l & _FPU_MASK_ALL) != 0)
(void)__fe_mask_env ();
/* Put the new state in effect. */ /* Put the new state in effect. */
fesetenv_register (new.fenv); fesetenv_register (new.fenv);

20
sysdeps/powerpc/fpu/fenv_libc.h
View File

@ -27,6 +27,26 @@ extern const fenv_t *__fe_nomask_env_priv (void);
extern const fenv_t *__fe_mask_env (void) attribute_hidden; extern const fenv_t *__fe_mask_env (void) attribute_hidden;
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
#define __TEST_AND_ENTER_NON_STOP(old, new) \
do { \
if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \
(void) __fe_mask_env (); \
} while (0)
/* If the old env has no enabled exceptions and the new env has any enabled
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
hardware into "precise mode" and may cause the FPU to run slower on some
hardware. */
#define __TEST_AND_EXIT_NON_STOP(old, new) \
do { \
if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \
(void) __fe_nomask_env_priv (); \
} while (0)
/* The sticky bits in the FPSCR indicating exceptions have occurred. */ /* The sticky bits in the FPSCR indicating exceptions have occurred. */
#define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID) #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)

83
sysdeps/powerpc/fpu/fenv_private.h
View File

@ -23,73 +23,20 @@
#include <fenv_libc.h> #include <fenv_libc.h>
#include <fpu_control.h> #include <fpu_control.h>
/* Mask for the exception enable bits. */
#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \
| _FPU_MASK_XM | _FPU_MASK_IM)
/* Mask the rounding mode bits. */
#define _FPU_MASK_RN 0xfffffffffffffffcLL
/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */
#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL
/* Mask restore rounding mode and exception enabled. */
#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL
/* Mask FP result flags, preserve fraction rounded/inexact bits. */
#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL
static __always_inline void static __always_inline void
__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask, libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
unsigned long long bits)
{ {
fenv_union_t old, new; fenv_union_t old, new;
old.fenv = *envp = fegetenv_register (); old.fenv = *envp = fegetenv_register ();
new.l = (old.l & mask) | bits; __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
/* If the old env had any enabled exceptions, then mask SIGFPE in the
MSR FE0/FE1 bits. This may allow the FPU to run faster because it
always takes the default action and can not generate SIGFPE. */
if ((old.l & _FPU_ALL_TRAPS) != 0)
(void) __fe_mask_env ();
/* Clear everything and set the rounding mode. */
new.l = r;
fesetenv_register (new.fenv); fesetenv_register (new.fenv);
} }
static __always_inline void
libc_feholdexcept_ppc (fenv_t *envp)
{
__libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL);
}
static __always_inline void
libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
{
__libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r);
}
static __always_inline void
libc_fesetround_ppc (int r)
{
__fesetround_inline (r);
}
static __always_inline int
libc_fetestexcept_ppc (int e)
{
fenv_union_t u;
u.fenv = fegetenv_register ();
return u.l & e;
}
static __always_inline void
libc_feholdsetround_ppc (fenv_t *e, int r)
{
__libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r);
}
static __always_inline unsigned long long static __always_inline unsigned long long
__libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
unsigned long long new_mask) unsigned long long new_mask)
@ -102,19 +49,8 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
/* Merge bits while masking unwanted bits from new and old env. */ /* Merge bits while masking unwanted bits from new and old env. */
new.l = (old.l & old_mask) | (new.l & new_mask); new.l = (old.l & old_mask) | (new.l & new_mask);
/* If the old env has no enabled exceptions and the new env has any enabled __TEST_AND_EXIT_NON_STOP (old.l, new.l);
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the __TEST_AND_ENTER_NON_STOP (old.l, new.l);
hardware into "precise mode" and may cause the FPU to run slower on some
hardware. */
if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0)
(void) __fe_nomask_env_priv ();
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0)
(void) __fe_mask_env ();
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */ /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
fesetenv_register (new.fenv); fesetenv_register (new.fenv);
@ -139,8 +75,8 @@ libc_feresetround_ppc (fenv_t *envp)
static __always_inline int static __always_inline int
libc_feupdateenv_test_ppc (fenv_t *envp, int ex) libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
{ {
return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN, return __libc_femergeenv_ppc (envp, ~FPSCR_CONTROL_MASK,
_FPU_MASK_FRAC_INEX_RET_CC) & ex; ~FPSCR_STATUS_MASK) & ex;
} }
static __always_inline void static __always_inline void
@ -193,8 +129,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r)
ctx->env = old.fenv; ctx->env = old.fenv;
if (__glibc_unlikely (new.l != old.l)) if (__glibc_unlikely (new.l != old.l))
{ {
if ((old.l & _FPU_ALL_TRAPS) != 0) __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
(void) __fe_mask_env ();
fesetenv_register (new.fenv); fesetenv_register (new.fenv);
ctx->updated_status = true; ctx->updated_status = true;
} }

15
sysdeps/powerpc/fpu/fesetenv.c
View File

@ -28,19 +28,8 @@ __fesetenv (const fenv_t *envp)
new.fenv = *envp; new.fenv = *envp;
old.fenv = fegetenv_status (); old.fenv = fegetenv_status ();
/* If the old env has no enabled exceptions and the new env has any enabled __TEST_AND_EXIT_NON_STOP (old.l, new.l);
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the __TEST_AND_ENTER_NON_STOP (old.l, new.l);
hardware into "precise mode" and may cause the FPU to run slower on some
hardware. */
if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
(void) __fe_nomask_env_priv ();
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
(void)__fe_mask_env ();
fesetenv_register (new.fenv); fesetenv_register (new.fenv);

7
sysdeps/powerpc/fpu/fesetmode.c
View File

@ -33,11 +33,8 @@ fesetmode (const femode_t *modep)
if (old.l == new.l) if (old.l == new.l)
return 0; return 0;
if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0) __TEST_AND_EXIT_NON_STOP (old.l, new.l);
(void) __fe_nomask_env_priv (); __TEST_AND_ENTER_NON_STOP (old.l, new.l);
if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
(void) __fe_mask_env ();
fesetenv_mode (new.fenv); fesetenv_mode (new.fenv);
return 0; return 0;

17
sysdeps/powerpc/fpu/feupdateenv.c
View File

@ -20,8 +20,6 @@
#include <fenv_libc.h> #include <fenv_libc.h>
#include <fpu_control.h> #include <fpu_control.h>
#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
int int
__feupdateenv (const fenv_t *envp) __feupdateenv (const fenv_t *envp)
{ {
@ -36,19 +34,8 @@ __feupdateenv (const fenv_t *envp)
unchanged. */ unchanged. */
new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff); new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff);
/* If the old env has no enabled exceptions and the new env has any enabled __TEST_AND_EXIT_NON_STOP (old.l, new.l);
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put __TEST_AND_ENTER_NON_STOP (old.l, new.l);
the hardware into "precise mode" and may cause the FPU to run slower on
some hardware. */
if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
(void) __fe_nomask_env_priv ();
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env ();
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */ /* Atomically enable and raise (if appropriate) exceptions set in `new'. */
fesetenv_register (new.fenv); fesetenv_register (new.fenv);