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sparc: M7 optimized memset/bzero
Support added to identify Sparc M7/T7/S7/M8/T8 processor capability. Performance tests run on Sparc S7 using new code and old niagara4 code. Optimizations for memset also apply to bzero as they share code. For memset/bzero, performance comparison with niagara4 code: For memset nonzero data, 256-1023 bytes - 60-90% gain (in cache); 5% gain (out of cache) 1K+ bytes - 80-260% gain (in cache); 40-80% gain (out of cache) For memset zero data (and bzero), 256-1023 bytes - 80-120% gain (in cache), 0% gain (out of cache) 1024+ bytes - 2-4x gain (in cache), 10-35% gain (out of cache) Tested in sparcv9-*-* and sparc64-*-* targets in both multi and non-multi arch configurations. Patrick McGehearty <patrick.mcgehearty@oracle.com> Adhemerval Zanella <adhemerval.zanella@linaro.org> * sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile (sysdeps_routines): Add memset-niagara7. * sysdeps/sparc/sparc64/multiarch/Makefile (sysdes_rotuines): Likewise. * sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S: New file. * sysdeps/sparc/sparc64/multiarch/memset-niagara7.S: Likewise. * sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c (__libc_ifunc_impl_list): Add __bzero_niagara7 and __memset_niagara7. * sysdeps/sparc/sparc64/multiarch/ifunc-memset.h (IFUNC_SELECTOR): Add niagara7 option. * NEWS: Mention sparc m7 optimized memcpy, mempcpy, memmove, and memset.
This commit is contained in:
Patrick McGehearty
Adhemerval Zanella
parent
1b6e07f8e0
commit
e6a1c5dc77
14
ChangeLog
14
ChangeLog
@ -1,6 +1,20 @@
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2017-12-14 Patrick McGehearty <patrick.mcgehearty@oracle.com>
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Adhemerval Zanella <adhemerval.zanella@linaro.org>
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* sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile
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(sysdeps_routines): Add memset-niagara7.
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* sysdeps/sparc/sparc64/multiarch/Makefile (sysdes_rotuines):
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Likewise.
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* sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S: New
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file.
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* sysdeps/sparc/sparc64/multiarch/memset-niagara7.S: Likewise.
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* sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c
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(__libc_ifunc_impl_list): Add __bzero_niagara7 and __memset_niagara7.
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* sysdeps/sparc/sparc64/multiarch/ifunc-memset.h (IFUNC_SELECTOR):
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Add niagara7 option.
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* NEWS: Mention sparc m7 optimized memcpy, mempcpy, memmove, and
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memset.
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* sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile
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(sysdeps_routines): Add memcpy-memmove-niagara7 and memmove-ultra1.
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* sysdeps/sparc/sparc64/multiarch/Makefile (sysdeps_routines):
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2
NEWS
2
NEWS
@ -52,6 +52,8 @@ Major new features:
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declares the functions pkey_alloc, pkey_free, pkey_mprotect, pkey_set,
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pkey_get.
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* Optimized memcpy, mempcpy, memmove, and memset for sparc M7.
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Deprecated and removed features, and other changes affecting compatibility:
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* On GNU/Linux, the obsolete Linux constant PTRACE_SEIZE_DEVEL is no longer
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@ -10,5 +10,5 @@ ifeq ($(subdir),string)
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sysdep_routines += memcpy-ultra3 memcpy-niagara1 memcpy-niagara2 \
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memset-niagara1 memcpy-niagara4 memset-niagara4 \
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memcpy-ultra1 memset-ultra1 memcpy-memmove-niagara7 \
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memmove-ultra1
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memmove-ultra1 memset-niagara7
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endif
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@ -0,0 +1,2 @@
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#define XCC icc
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#include <sparc64/multiarch/memset-niagara7.S>
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@ -10,7 +10,7 @@ ifeq ($(subdir),string)
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sysdep_routines += memcpy-ultra3 memcpy-niagara1 memcpy-niagara2 \
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memset-niagara1 memcpy-niagara4 memset-niagara4 \
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memcpy-ultra1 memset-ultra1 memcpy-memmove-niagara7 \
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memmove-ultra1
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memmove-ultra1 memset-niagara7
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endif
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ifeq ($(subdir),stdlib)
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@ -62,6 +62,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL_ADD (array, i, mempcpy, 1, __mempcpy_ultra1));
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IFUNC_IMPL (i, name, bzero,
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IFUNC_IMPL_ADD (array, i, bzero, hwcap & HWCAP_SPARC_ADP,
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__bzero_niagara7)
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IFUNC_IMPL_ADD (array, i, bzero, hwcap & HWCAP_SPARC_CRYPTO,
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__bzero_niagara4)
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IFUNC_IMPL_ADD (array, i, bzero, hwcap & HWCAP_SPARC_BLKINIT,
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@ -69,6 +71,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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IFUNC_IMPL_ADD (array, i, bzero, 1, __bzero_ultra1));
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IFUNC_IMPL (i, name, memset,
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IFUNC_IMPL_ADD (array, i, memset, hwcap & HWCAP_SPARC_ADP,
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__memset_niagara7)
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IFUNC_IMPL_ADD (array, i, memset, hwcap & HWCAP_SPARC_CRYPTO,
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__memset_niagara4)
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IFUNC_IMPL_ADD (array, i, memset, hwcap & HWCAP_SPARC_BLKINIT,
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@ -19,6 +19,7 @@
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#include <ifunc-init.h>
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extern __typeof (REDIRECT_NAME) OPTIMIZE (niagara7) attribute_hidden;
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extern __typeof (REDIRECT_NAME) OPTIMIZE (niagara4) attribute_hidden;
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extern __typeof (REDIRECT_NAME) OPTIMIZE (niagara1) attribute_hidden;
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extern __typeof (REDIRECT_NAME) OPTIMIZE (ultra1) attribute_hidden;
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@ -26,6 +27,8 @@ extern __typeof (REDIRECT_NAME) OPTIMIZE (ultra1) attribute_hidden;
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static inline void *
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IFUNC_SELECTOR (int hwcap)
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{
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if (hwcap & HWCAP_SPARC_ADP)
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return OPTIMIZE (niagara7);
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if (hwcap & HWCAP_SPARC_CRYPTO)
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return OPTIMIZE (niagara4);
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if (hwcap & HWCAP_SPARC_BLKINIT)
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334
sysdeps/sparc/sparc64/multiarch/memset-niagara7.S
Normal file
334
sysdeps/sparc/sparc64/multiarch/memset-niagara7.S
Normal file
@ -0,0 +1,334 @@
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/* Set a block of memory to some byte value. For SUN4V M7.
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Copyright (C) 2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#ifndef XCC
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# define XCC xcc
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#endif
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.register %g2, #scratch
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.register %g3, #scratch
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/* The algorithm is as follows :
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*
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* For small 7 or fewer bytes stores, bytes will be stored.
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*
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* For less than 32 bytes stores, align the address on 4 byte boundary.
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* Then store as many 4-byte chunks, followed by trailing bytes.
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*
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* For sizes greater than 32 bytes, align the address on 8 byte boundary.
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* if (count >= 64) {
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* store 8-bytes chunks to align the address on 64 byte boundary
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* if (value to be set is zero && count >= MIN_ZERO) {
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* Using BIS stores, set the first long word of each
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* 64-byte cache line to zero which will also clear the
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* other seven long words of the cache line.
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* }
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* else if (count >= MIN_LOOP) {
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* Using BIS stores, set the first long word of each of
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* ST_CHUNK cache lines (64 bytes each) before the main
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* loop is entered.
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* In the main loop, continue pre-setting the first long
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* word of each cache line ST_CHUNK lines in advance while
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* setting the other seven long words (56 bytes) of each
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* cache line until fewer than ST_CHUNK*64 bytes remain.
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* Then set the remaining seven long words of each cache
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* line that has already had its first long word set.
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* }
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* store remaining data in 64-byte chunks until less than
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* 64 bytes remain.
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* }
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* Store as many 8-byte chunks, followed by trailing bytes.
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*
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*
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* BIS = Block Init Store
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* Doing the advance store of the first element of the cache line
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* initiates the displacement of a cache line while only using a single
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* instruction in the pipeline. That avoids various pipeline delays,
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* such as filling the miss buffer. The performance effect is
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* similar to prefetching for normal stores.
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* The special case for zero fills runs faster and uses fewer instruction
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* cycles than the normal memset loop.
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*
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* We only use BIS for memset of greater than MIN_LOOP bytes because a sequence
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* BIS stores must be followed by a membar #StoreStore. The benefit of
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* the BIS store must be balanced against the cost of the membar operation.
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*/
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/*
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* ASI_STBI_P marks the cache line as "least recently used"
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* which means if many threads are active, it has a high chance
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* of being pushed out of the cache between the first initializing
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* store and the final stores.
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* Thus, we use ASI_STBIMRU_P which marks the cache line as
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* "most recently used" for all but the last store to the cache line.
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*/
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#define ASI_BLK_INIT_QUAD_LDD_P 0xe2
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#define ASI_ST_BLK_INIT_MRU_P 0xf2
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#define ASI_STBI_P ASI_BLK_INIT_QUAD_LDD_P
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#define ASI_STBIMRU_P ASI_ST_BLK_INIT_MRU_P
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#define ST_CHUNK 24 /* multiple of 4 due to loop unrolling */
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#define MIN_LOOP (ST_CHUNK)*64
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#define MIN_ZERO 256
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#define EX_ST(x) x
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#define EX_RETVAL(x) x
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#define STORE_ASI(src,addr) stxa src, [addr] ASI_STBIMRU_P
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#define STORE_INIT(src,addr) stxa src, [addr] ASI_STBI_P
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#if IS_IN (libc)
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.text
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.align 32
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ENTRY(__bzero_niagara7)
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/* bzero (dst, size) */
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mov %o1, %o2
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mov 0, %o1
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/* fall through into memset code */
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END(__bzero_niagara7)
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ENTRY(__memset_niagara7)
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/* memset (src, c, size) */
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mov %o0, %o5 /* copy sp1 before using it */
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cmp %o2, 7 /* if small counts, just write bytes */
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bleu,pn %XCC, .Lwrchar
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and %o1, 0xff, %o1 /* o1 is (char)c */
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sll %o1, 8, %o3
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or %o1, %o3, %o1 /* now o1 has 2 bytes of c */
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sll %o1, 16, %o3
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cmp %o2, 32
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blu,pn %XCC, .Lwdalign
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or %o1, %o3, %o1 /* now o1 has 4 bytes of c */
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sllx %o1, 32, %o3
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or %o1, %o3, %o1 /* now o1 has 8 bytes of c */
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.Ldbalign:
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andcc %o5, 7, %o3 /* is sp1 aligned on a 8 byte bound? */
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bz,pt %XCC, .Lblkalign /* already long word aligned */
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sub %o3, 8, %o3 /* -(bytes till long word aligned) */
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add %o2, %o3, %o2 /* update o2 with new count */
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/* Set -(%o3) bytes till sp1 long word aligned */
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1: stb %o1, [%o5] /* there is at least 1 byte to set */
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inccc %o3 /* byte clearing loop */
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bl,pt %XCC, 1b
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inc %o5
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/* Now sp1 is long word aligned (sp1 is found in %o5) */
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.Lblkalign:
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cmp %o2, 64 /* check if there are 64 bytes to set */
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blu,pn %XCC, .Lwrshort
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mov %o2, %o3
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andcc %o5, 63, %o3 /* is sp1 block aligned? */
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bz,pt %XCC, .Lblkwr /* now block aligned */
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sub %o3, 64, %o3 /* o3 is -(bytes till block aligned) */
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add %o2, %o3, %o2 /* o2 is the remainder */
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/* Store -(%o3) bytes till dst is block (64 byte) aligned. */
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/* Use long word stores. */
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/* Recall that dst is already long word aligned */
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1:
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addcc %o3, 8, %o3
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stx %o1, [%o5]
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bl,pt %XCC, 1b
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add %o5, 8, %o5
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/* Now sp1 is block aligned */
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.Lblkwr:
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andn %o2, 63, %o4 /* calculate size of blocks in bytes */
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brz,pn %o1, .Lwrzero /* special case if c == 0 */
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and %o2, 63, %o3 /* %o3 = bytes left after blk stores */
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cmp %o4, MIN_LOOP /* check for enough bytes to set */
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blu,pn %XCC, .Lshort_set /* to justify cost of membar */
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nop /* must be > pre-cleared lines */
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/* initial cache-clearing stores */
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/* get store pipeline moving */
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/* Primary memset loop for large memsets */
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.Lwr_loop:
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mov ST_CHUNK, %g1
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.Lwr_loop_start:
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subcc %g1, 4, %g1
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EX_ST(STORE_ASI(%o1,%o5))
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add %o5, 64, %o5
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EX_ST(STORE_ASI(%o1,%o5))
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add %o5, 64, %o5
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EX_ST(STORE_ASI(%o1,%o5))
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add %o5, 64, %o5
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EX_ST(STORE_ASI(%o1,%o5))
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bgu %XCC, .Lwr_loop_start
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add %o5, 64, %o5
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sub %o5, ST_CHUNK*64, %o5 /* reset %o5 */
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mov ST_CHUNK, %g1
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sub %o5, 8, %o5 /* adjust %o5 for ASI store */
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.Lwr_loop_rest:
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stx %o1,[%o5+8+8]
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sub %o4, 64, %o4
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stx %o1,[%o5+16+8]
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subcc %g1, 1, %g1
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stx %o1,[%o5+24+8]
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stx %o1,[%o5+32+8]
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stx %o1,[%o5+40+8]
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add %o5, 64, %o5
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stx %o1,[%o5-8]
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bgu %XCC, .Lwr_loop_rest
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EX_ST(STORE_INIT(%o1,%o5))
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add %o5, 8, %o5 /* restore %o5 offset */
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/* If more than ST_CHUNK*64 bytes remain to set, continue */
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/* setting the first long word of each cache line in advance */
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/* to keep the store pipeline moving. */
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cmp %o4, ST_CHUNK*64
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bge,pt %XCC, .Lwr_loop_start
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mov ST_CHUNK, %g1
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brz,a,pn %o4, .Lasi_done
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nop
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sub %o5, 8, %o5 /* adjust %o5 for ASI store */
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.Lwr_loop_small:
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add %o5, 8, %o5 /* adjust %o5 for ASI store */
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EX_ST(STORE_ASI(%o1,%o5))
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stx %o1,[%o5+8]
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stx %o1,[%o5+16]
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stx %o1,[%o5+24]
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stx %o1,[%o5+32]
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subcc %o4, 64, %o4
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stx %o1,[%o5+40]
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add %o5, 56, %o5
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stx %o1,[%o5-8]
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bgu,pt %XCC, .Lwr_loop_small
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EX_ST(STORE_INIT(%o1,%o5))
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ba .Lasi_done
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add %o5, 8, %o5 /* restore %o5 offset */
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/* Special case loop for zero fill memsets */
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/* For each 64 byte cache line, single STBI to first element */
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/* clears line */
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.Lwrzero:
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cmp %o4, MIN_ZERO /* check if enough bytes to set */
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/* to pay %asi + membar cost */
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blu %XCC, .Lshort_set
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nop
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sub %o4, 256, %o4
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.Lwrzero_loop:
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mov 64, %g3
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EX_ST(STORE_INIT(%o1,%o5))
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subcc %o4, 256, %o4
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EX_ST(STORE_INIT(%o1,%o5+%g3))
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add %o5, 256, %o5
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sub %g3, 192, %g3
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EX_ST(STORE_INIT(%o1,%o5+%g3))
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add %g3, 64, %g3
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bge,pt %XCC, .Lwrzero_loop
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EX_ST(STORE_INIT(%o1,%o5+%g3))
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add %o4, 256, %o4
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brz,pn %o4, .Lbsi_done
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nop
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.Lwrzero_small:
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EX_ST(STORE_INIT(%o1,%o5))
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subcc %o4, 64, %o4
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bgu,pt %XCC, .Lwrzero_small
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add %o5, 64, %o5
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.Lasi_done:
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.Lbsi_done:
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membar #StoreStore /* required by use of BSI */
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.Lshort_set:
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cmp %o4, 64 /* check if 64 bytes to set */
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blu %XCC, 5f
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nop
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4: /* set final blocks of 64 bytes */
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stx %o1, [%o5]
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stx %o1, [%o5+8]
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stx %o1, [%o5+16]
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stx %o1, [%o5+24]
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subcc %o4, 64, %o4
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stx %o1, [%o5+32]
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stx %o1, [%o5+40]
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add %o5, 64, %o5
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stx %o1, [%o5-16]
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bgu,pt %XCC, 4b
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stx %o1, [%o5-8]
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5:
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/* Set the remaining long words */
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.Lwrshort:
|
||||
subcc %o3, 8, %o3 /* Can we store any long words? */
|
||||
blu,pn %XCC, .Lwrchars
|
||||
and %o2, 7, %o2 /* calc bytes left after long words */
|
||||
6:
|
||||
subcc %o3, 8, %o3
|
||||
stx %o1, [%o5] /* store the long words */
|
||||
bgeu,pt %XCC, 6b
|
||||
add %o5, 8, %o5
|
||||
|
||||
.Lwrchars: /* check for extra chars */
|
||||
brnz %o2, .Lwrfin
|
||||
nop
|
||||
retl
|
||||
nop
|
||||
|
||||
.Lwdalign:
|
||||
andcc %o5, 3, %o3 /* is sp1 aligned on a word boundary */
|
||||
bz,pn %XCC, .Lwrword
|
||||
andn %o2, 3, %o3 /* create word sized count in %o3 */
|
||||
|
||||
dec %o2 /* decrement count */
|
||||
stb %o1, [%o5] /* clear a byte */
|
||||
b .Lwdalign
|
||||
inc %o5 /* next byte */
|
||||
|
||||
.Lwrword:
|
||||
subcc %o3, 4, %o3
|
||||
st %o1, [%o5] /* 4-byte writing loop */
|
||||
bnz,pt %XCC, .Lwrword
|
||||
add %o5, 4, %o5
|
||||
and %o2, 3, %o2 /* leftover count, if any */
|
||||
|
||||
.Lwrchar:
|
||||
/* Set the remaining bytes, if any */
|
||||
brz %o2, .Lexit
|
||||
nop
|
||||
.Lwrfin:
|
||||
deccc %o2
|
||||
stb %o1, [%o5]
|
||||
bgu,pt %XCC, .Lwrfin
|
||||
inc %o5
|
||||
.Lexit:
|
||||
retl /* %o0 was preserved */
|
||||
nop
|
||||
END(__memset_niagara7)
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user