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S390: Do not set FE_INEXACT with feraiseexcept (FE_OWERFLOW|FE_UNDERFLOW).
On s390 feraiseexcept (FE_OVERFLOW|FE_UNDERFLOW) sets FE_INEXACT, too. This patch uses z196 zarch load rounded instruction which can suppress FE_INEXACT exception if gcc has z196 support in used configuration. Otherwise FE_INEXACT flag is set as before. The gcc support is tested in a new configure-check. A comment in fsetexcptflg.c is corrected as new exceptions are not executed with the next floating-point instruction if fpc is set with _FPU_SETCW macro. It seems the comment was copied e.g. from sysdeps/x86_64/fpu/fsetexcptflg.c file. ChangeLog: * config.h.in (HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT): New undefine. * sysdeps/s390/configure.ac: Add test for z196 zarch support. * sysdeps/s390/configure: Regenerated. * sysdeps/s390/fpu/fraiseexcpt.c (__feraiseexcept): Use ledbra instruction for raising over-/underflow if z196 zarch is supported by default. * sysdeps/s390/fpu/fsetexcptflg.c (fesetexceptflag): Correct comment.
This commit is contained in:
Stefan Liebler
parent
aaf3045480
commit
e9b424881a
10
ChangeLog
10
ChangeLog
@ -1,3 +1,13 @@
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2016-08-31 Stefan Liebler <stli@linux.vnet.ibm.com>
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* config.h.in (HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT): New undefine.
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* sysdeps/s390/configure.ac: Add test for z196 zarch support.
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* sysdeps/s390/configure: Regenerated.
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* sysdeps/s390/fpu/fraiseexcpt.c (__feraiseexcept): Use ledbra
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instruction for raising over-/underflow if z196 zarch is supported
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by default.
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* sysdeps/s390/fpu/fsetexcptflg.c (fesetexceptflag): Correct comment.
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2016-08-30 Svante Signell <svante.signell@gmail.com>
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* sysdeps/mach/hurd/adjtime.c (__adjtime): When OLDDELTA is NULL, make
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@ -70,6 +70,9 @@
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/* Define if assembler supports AVX512DQ. */
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#undef HAVE_AVX512DQ_ASM_SUPPORT
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/* Define if assembler supports z196 zarch instructions as default on S390. */
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#undef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
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/* Define if assembler supports vector instructions on S390. */
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#undef HAVE_S390_VX_ASM_SUPPORT
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36
sysdeps/s390/configure
vendored
36
sysdeps/s390/configure
vendored
@ -177,5 +177,41 @@ then
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fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for S390 z196 zarch instruction support as default" >&5
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$as_echo_n "checking for S390 z196 zarch instruction support as default... " >&6; }
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if ${libc_cv_asm_s390_min_z196_zarch+:} false; then :
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$as_echo_n "(cached) " >&6
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else
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cat > conftest.c <<\EOF
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float testinsn (double e)
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{
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float d;
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__asm__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) );
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return d;
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}
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EOF
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if { ac_try='${CC-cc} $CFLAGS $CPPFLAGS $LDFLAGS --shared conftest.c
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-o conftest.o &> /dev/null'
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{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
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(eval $ac_try) 2>&5
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ac_status=$?
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$as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
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test $ac_status = 0; }; } ;
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then
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libc_cv_asm_s390_min_z196_zarch=yes
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else
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libc_cv_asm_s390_min_z196_zarch=no
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fi
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rm -f conftest*
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fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_s390_min_z196_zarch" >&5
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$as_echo "$libc_cv_asm_s390_min_z196_zarch" >&6; }
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if test "$libc_cv_asm_s390_min_z196_zarch" = yes ;
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then
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$as_echo "#define HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT 1" >>confdefs.h
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fi
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test -n "$critic_missing" && as_fn_error $? "
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*** $critic_missing" "$LINENO" 5
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@ -86,5 +86,31 @@ then
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AC_DEFINE(HAVE_S390_VX_GCC_SUPPORT)
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fi
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AC_CACHE_CHECK(for S390 z196 zarch instruction support as default,
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libc_cv_asm_s390_min_z196_zarch, [dnl
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cat > conftest.c <<\EOF
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float testinsn (double e)
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{
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float d;
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__asm__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) );
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return d;
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}
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EOF
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dnl
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dnl test, if assembler supports S390 z196 zarch instructions as default
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if AC_TRY_COMMAND([${CC-cc} $CFLAGS $CPPFLAGS $LDFLAGS --shared conftest.c
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-o conftest.o &> /dev/null]) ;
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then
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libc_cv_asm_s390_min_z196_zarch=yes
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else
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libc_cv_asm_s390_min_z196_zarch=no
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fi
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rm -f conftest* ])
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if test "$libc_cv_asm_s390_min_z196_zarch" = yes ;
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then
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AC_DEFINE(HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT)
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fi
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test -n "$critic_missing" && AC_MSG_ERROR([
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*** $critic_missing])
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@ -35,6 +35,23 @@ fexceptadd (float d, float e)
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__asm__ __volatile__ ("aebr %0,%1" : : "f" (d), "f" (e) );
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}
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#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
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static __inline__ void
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fexceptround (double e)
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{
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float d;
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/* Load rounded from double to float with M3 = round toward 0, M4 = Suppress
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IEEE-inexact exception.
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In case of e=0x1p128 and the overflow-mask bit is zero, only the
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IEEE-overflow flag is set. If overflow-mask bit is one, DXC field is set to
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0x20 "IEEE overflow, exact".
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In case of e=0x1p-150 and the underflow-mask bit is zero, only the
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IEEE-underflow flag is set. If underflow-mask bit is one, DXC field is set
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to 0x10 "IEEE underflow, exact".
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This instruction is available with a zarch machine >= z196. */
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__asm__ __volatile__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) );
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}
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#endif
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int
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__feraiseexcept (int excepts)
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@ -54,13 +71,29 @@ __feraiseexcept (int excepts)
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/* Next: overflow. */
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if (FE_OVERFLOW & excepts)
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/* I don't think we can do the same trick as intel so we will have
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to live with inexact coming also. */
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fexceptadd (FLT_MAX, 1.0e32);
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{
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#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
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fexceptround (0x1p128);
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#else
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/* If overflow-mask bit is zero, both IEEE-overflow and IEEE-inexact flags
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are set. If overflow-mask bit is one, DXC field is set to 0x2C "IEEE
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overflow, inexact and incremented". */
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fexceptadd (FLT_MAX, 1.0e32);
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#endif
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}
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/* Next: underflow. */
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if (FE_UNDERFLOW & excepts)
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fexceptdiv (FLT_MIN, 3.0);
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{
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#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
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fexceptround (0x1p-150);
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#else
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/* If underflow-mask bit is zero, both IEEE-underflow and IEEE-inexact
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flags are set. If underflow-mask bit is one, DXC field is set to 0x1C
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"IEEE underflow, inexact and incremented". */
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fexceptdiv (FLT_MIN, 3.0);
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#endif
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}
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/* Last: inexact. */
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if (FE_INEXACT & excepts)
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@ -45,8 +45,7 @@ fesetexceptflag (const fexcept_t *flagp, int excepts)
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& newexcepts;
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/* Store the new status word (along with the rest of the environment.
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Possibly new exceptions are set but they won't get executed unless
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the next floating-point instruction. */
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Possibly new exceptions are set but they won't get executed. */
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_FPU_SETCW (temp);
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/* Success. */
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