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Update.
* sysdeps/powerpc/powerpc64/bits/atomic.h: Never use matching constraints for asm mem parameters. * sysdeps/powerpc/bits/atomic.h: Likewise.
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@ -1,5 +1,9 @@
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2004-04-03 Ulrich Drepper <drepper@redhat.com>
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* sysdeps/powerpc/powerpc64/bits/atomic.h: Never use matching
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constraints for asm mem parameters.
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* sysdeps/powerpc/bits/atomic.h: Likewise.
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* sysdeps/powerpc/elf/libc-start.c: no need for a separate
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function for __aux_init_cache.
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@ -1,5 +1,5 @@
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/* Atomic operations. PowerPC Common version.
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Copyright (C) 2003 Free Software Foundation, Inc.
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Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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@ -53,7 +53,7 @@ typedef uintmax_t uatomic_max_t;
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#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \
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(abort (), 0)
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@ -116,7 +116,7 @@ typedef uintmax_t uatomic_max_t;
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" bne- 1b\n" \
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" " __ARCH_ACQ_INSTR \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "1" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -129,7 +129,7 @@ typedef uintmax_t uatomic_max_t;
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" stwcx. %3,0,%2\n" \
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" bne- 1b" \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "1" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -142,7 +142,7 @@ typedef uintmax_t uatomic_max_t;
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" stwcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "2" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -157,7 +157,7 @@ typedef uintmax_t uatomic_max_t;
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "2" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -173,7 +173,7 @@ typedef uintmax_t uatomic_max_t;
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abort (); \
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__result; \
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})
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#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __result; \
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@ -1,5 +1,5 @@
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/* Atomic operations. PowerPC64 version.
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Copyright (C) 2003 Free Software Foundation, Inc.
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Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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@ -61,8 +61,8 @@
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__tmp != 0; \
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})
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/*
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* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
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/*
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* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
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* and Store doubleword conditional indexed (stdcx) instructions. So here
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* we define the 64-bit forms.
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*/
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@ -141,7 +141,7 @@
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" bne- 1b\n" \
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" " __ARCH_ACQ_INSTR \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "1" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -154,7 +154,7 @@
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" stdcx. %3,0,%2\n" \
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" bne- 1b" \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "1" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -167,7 +167,7 @@
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" stdcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "2" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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@ -182,17 +182,17 @@
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "2" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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/*
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* All powerpc64 processors support the new "light weight" sync (lwsync).
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/*
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* All powerpc64 processors support the new "light weight" sync (lwsync).
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*/
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# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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# ifndef UP
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# define __ARCH_REL_INSTR "lwsync"
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@ -200,6 +200,6 @@
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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* powerpc32 and powerpc64.
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*/
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#include_next <bits/atomic.h>
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