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powerpc64: Check cacheline size before using optimised memset routines

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A number of optimised memset routines assume the cacheline size is 128B,
so we better check before using them.

Reviewed-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2021-07-27 15:47:50 +10:00 committed by Tulio Magno Quites Machado Filho
parent e4ca6de1bc
commit f2a15dd668
2 changed files with 23 additions and 10 deletions
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18
sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
View File

@ -35,6 +35,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
unsigned long int hwcap = GLRO(dl_hwcap);
unsigned long int hwcap2 = GLRO(dl_hwcap2);
#ifdef SHARED
int cacheline_size = GLRO(dl_cache_line_size);
#endif
/* hwcap contains only the latest supported ISA, the code checks which is
and fills the previous supported ones. */
@ -90,16 +93,21 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
IFUNC_IMPL_ADD (array, i, memset,
hwcap2 & PPC_FEATURE2_ARCH_3_1
&& hwcap2 & PPC_FEATURE2_HAS_ISEL
&& hwcap & PPC_FEATURE_HAS_VSX,
&& hwcap & PPC_FEATURE_HAS_VSX
&& cacheline_size == 128,
__memset_power10)
#endif
IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07,
IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07
&& cacheline_size == 128,
__memset_power8)
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_06,
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_06
&& cacheline_size == 128,
__memset_power7)
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_05,
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_05
&& cacheline_size == 128,
__memset_power6)
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_POWER4,
IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_POWER4
&& cacheline_size == 128,
__memset_power4)
IFUNC_IMPL_ADD (array, i, memset, 1, __memset_ppc))

15
sysdeps/powerpc/powerpc64/multiarch/memset.c
View File

@ -43,16 +43,21 @@ libc_ifunc (__libc_memset,
# ifdef __LITTLE_ENDIAN__
(hwcap2 & PPC_FEATURE2_ARCH_3_1
&& hwcap2 & PPC_FEATURE2_HAS_ISEL
&& hwcap & PPC_FEATURE_HAS_VSX)
&& hwcap & PPC_FEATURE_HAS_VSX
&& GLRO(dl_cache_line_size) == 128)
? __memset_power10 :
# endif
(hwcap2 & PPC_FEATURE2_ARCH_2_07)
(hwcap2 & PPC_FEATURE2_ARCH_2_07
&& GLRO(dl_cache_line_size) == 128)
? __memset_power8 :
(hwcap & PPC_FEATURE_ARCH_2_06)
(hwcap & PPC_FEATURE_ARCH_2_06
&& GLRO(dl_cache_line_size) == 128)
? __memset_power7 :
(hwcap & PPC_FEATURE_ARCH_2_05)
(hwcap & PPC_FEATURE_ARCH_2_05
&& GLRO(dl_cache_line_size) == 128)
? __memset_power6 :
(hwcap & PPC_FEATURE_POWER4)
(hwcap & PPC_FEATURE_POWER4
&& GLRO(dl_cache_line_size) == 128)
? __memset_power4
: __memset_ppc);