AuroraMiddleware/glibc
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Optimize to reduce FPCR/FPSR accesses.

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Wilco Dijkstra 2014-12-22 17:07:16 +00:00
parent 9b47df5814
commit f3806bdbc1
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@ -1,3 +1,8 @@
2014-12-22 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/fpu/fesetenv.c (fesetenv):
Optimize to reduce FPCR/FPSR accesses.
2014-12-22 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/fpu/ftestexcept.c (fetestexcept):