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Set index_arch_AVX_Fast_Unaligned_Load only for Intel processors
Since only Intel processors with AVX2 have fast unaligned load, we should set index_arch_AVX_Fast_Unaligned_Load only for Intel processors. Move AVX, AVX2, AVX512, FMA and FMA4 detection into get_common_indeces and call get_common_indeces for other processors. Add CPU_FEATURES_CPU_P and CPU_FEATURES_ARCH_P to aoid loading GLRO(dl_x86_cpu_features) in cpu-features.c. [BZ #19583] * sysdeps/x86/cpu-features.c (get_common_indeces): Remove inline. Check family before setting family, model and extended_model. Set AVX, AVX2, AVX512, FMA and FMA4 usable bits here. (init_cpu_features): Replace HAS_CPU_FEATURE and HAS_ARCH_FEATURE with CPU_FEATURES_CPU_P and CPU_FEATURES_ARCH_P. Set index_arch_AVX_Fast_Unaligned_Load for Intel processors with usable AVX2. Call get_common_indeces for other processors with family == NULL. * sysdeps/x86/cpu-features.h (CPU_FEATURES_CPU_P): New macro. (CPU_FEATURES_ARCH_P): Likewise. (HAS_CPU_FEATURE): Use CPU_FEATURES_CPU_P. (HAS_ARCH_FEATURE): Use CPU_FEATURES_ARCH_P.
This commit is contained in:
H.J. Lu
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17
ChangeLog
17
ChangeLog
@ -1,3 +1,20 @@
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2016-03-22 H.J. Lu <hongjiu.lu@intel.com>
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[BZ #19583]
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* sysdeps/x86/cpu-features.c (get_common_indeces): Remove
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inline. Check family before setting family, model and
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extended_model. Set AVX, AVX2, AVX512, FMA and FMA4 usable
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bits here.
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(init_cpu_features): Replace HAS_CPU_FEATURE and
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HAS_ARCH_FEATURE with CPU_FEATURES_CPU_P and
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CPU_FEATURES_ARCH_P. Set index_arch_AVX_Fast_Unaligned_Load
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for Intel processors with usable AVX2. Call get_common_indeces
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for other processors with family == NULL.
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* sysdeps/x86/cpu-features.h (CPU_FEATURES_CPU_P): New macro.
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(CPU_FEATURES_ARCH_P): Likewise.
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(HAS_CPU_FEATURE): Use CPU_FEATURES_CPU_P.
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(HAS_ARCH_FEATURE): Use CPU_FEATURES_ARCH_P.
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2016-03-22 Samuel Thibault <samuel.thibault@ens-lyon.org>
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* malloc/Makefile ($(objpfx)tst-malloc-backtrace,
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@ -19,23 +19,79 @@
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#include <cpuid.h>
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#include <cpu-features.h>
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static inline void
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static void
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get_common_indeces (struct cpu_features *cpu_features,
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unsigned int *family, unsigned int *model,
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unsigned int *extended_model)
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{
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unsigned int eax;
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__cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
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GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].eax = eax;
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*family = (eax >> 8) & 0x0f;
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*model = (eax >> 4) & 0x0f;
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*extended_model = (eax >> 12) & 0xf0;
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if (*family == 0x0f)
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if (family)
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{
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*family += (eax >> 20) & 0xff;
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*model += *extended_model;
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unsigned int eax;
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__cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
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cpu_features->cpuid[COMMON_CPUID_INDEX_1].eax = eax;
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*family = (eax >> 8) & 0x0f;
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*model = (eax >> 4) & 0x0f;
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*extended_model = (eax >> 12) & 0xf0;
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if (*family == 0x0f)
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{
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*family += (eax >> 20) & 0xff;
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*model += *extended_model;
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}
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}
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if (cpu_features->max_cpuid >= 7)
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__cpuid_count (7, 0,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
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/* Can we call xgetbv? */
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if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE))
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{
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unsigned int xcrlow;
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unsigned int xcrhigh;
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asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
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/* Is YMM and XMM state usable? */
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if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
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(bit_YMM_state | bit_XMM_state))
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{
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/* Determine if AVX is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX))
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cpu_features->feature[index_arch_AVX_Usable]
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|= bit_arch_AVX_Usable;
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/* Determine if AVX2 is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX2))
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cpu_features->feature[index_arch_AVX2_Usable]
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|= bit_arch_AVX2_Usable;
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/* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
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ZMM16-ZMM31 state are enabled. */
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if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
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| bit_ZMM16_31_state)) ==
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(bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
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{
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/* Determine if AVX512F is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512F))
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{
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cpu_features->feature[index_arch_AVX512F_Usable]
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|= bit_arch_AVX512F_Usable;
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/* Determine if AVX512DQ is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512DQ))
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cpu_features->feature[index_arch_AVX512DQ_Usable]
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|= bit_arch_AVX512DQ_Usable;
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}
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}
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/* Determine if FMA is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, FMA))
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cpu_features->feature[index_arch_FMA_Usable]
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|= bit_arch_FMA_Usable;
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/* Determine if FMA4 is usable. */
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if (CPU_FEATURES_CPU_P (cpu_features, FMA4))
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cpu_features->feature[index_arch_FMA4_Usable]
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|= bit_arch_FMA4_Usable;
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}
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}
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}
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@ -135,6 +191,12 @@ init_cpu_features (struct cpu_features *cpu_features)
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break;
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}
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}
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/* Unaligned load with 256-bit AVX registers are faster on
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Intel processors with AVX2. */
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if (CPU_FEATURES_ARCH_P (cpu_features, AVX2_Usable))
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cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
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|= bit_arch_AVX_Fast_Unaligned_Load;
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}
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/* This spells out "AuthenticAMD". */
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else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
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@ -165,73 +227,19 @@ init_cpu_features (struct cpu_features *cpu_features)
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}
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}
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else
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kind = arch_kind_other;
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{
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kind = arch_kind_other;
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get_common_indeces (cpu_features, NULL, NULL, NULL);
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}
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/* Support i586 if CX8 is available. */
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if (HAS_CPU_FEATURE (CX8))
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if (CPU_FEATURES_CPU_P (cpu_features, CX8))
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cpu_features->feature[index_arch_I586] |= bit_arch_I586;
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/* Support i686 if CMOV is available. */
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if (HAS_CPU_FEATURE (CMOV))
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if (CPU_FEATURES_CPU_P (cpu_features, CMOV))
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cpu_features->feature[index_arch_I686] |= bit_arch_I686;
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if (cpu_features->max_cpuid >= 7)
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__cpuid_count (7, 0,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
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cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
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/* Can we call xgetbv? */
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if (HAS_CPU_FEATURE (OSXSAVE))
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{
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unsigned int xcrlow;
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unsigned int xcrhigh;
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asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
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/* Is YMM and XMM state usable? */
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if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
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(bit_YMM_state | bit_XMM_state))
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{
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/* Determine if AVX is usable. */
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if (HAS_CPU_FEATURE (AVX))
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cpu_features->feature[index_arch_AVX_Usable]
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|= bit_arch_AVX_Usable;
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#if index_arch_AVX2_Usable != index_arch_AVX_Fast_Unaligned_Load
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# error index_arch_AVX2_Usable != index_arch_AVX_Fast_Unaligned_Load
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#endif
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/* Determine if AVX2 is usable. Unaligned load with 256-bit
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AVX registers are faster on processors with AVX2. */
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if (HAS_CPU_FEATURE (AVX2))
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cpu_features->feature[index_arch_AVX2_Usable]
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|= bit_arch_AVX2_Usable | bit_arch_AVX_Fast_Unaligned_Load;
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/* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
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ZMM16-ZMM31 state are enabled. */
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if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
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| bit_ZMM16_31_state)) ==
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(bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
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{
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/* Determine if AVX512F is usable. */
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if (HAS_CPU_FEATURE (AVX512F))
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{
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cpu_features->feature[index_arch_AVX512F_Usable]
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|= bit_arch_AVX512F_Usable;
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/* Determine if AVX512DQ is usable. */
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if (HAS_CPU_FEATURE (AVX512DQ))
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cpu_features->feature[index_arch_AVX512DQ_Usable]
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|= bit_arch_AVX512DQ_Usable;
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}
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}
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/* Determine if FMA is usable. */
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if (HAS_CPU_FEATURE (FMA))
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cpu_features->feature[index_arch_FMA_Usable]
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|= bit_arch_FMA_Usable;
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/* Determine if FMA4 is usable. */
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if (HAS_CPU_FEATURE (FMA4))
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cpu_features->feature[index_arch_FMA4_Usable]
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|= bit_arch_FMA4_Usable;
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}
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}
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#if !HAS_CPUID
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no_cpuid:
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#endif
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@ -204,11 +204,17 @@ extern const struct cpu_features *__get_cpu_features (void)
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# endif
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/* Only used directly in cpu-features.c. */
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# define CPU_FEATURES_CPU_P(ptr, name) \
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((ptr->cpuid[index_cpu_##name].reg_##name & (bit_cpu_##name)) != 0)
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# define CPU_FEATURES_ARCH_P(ptr, name) \
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((ptr->feature[index_arch_##name] & (bit_arch_##name)) != 0)
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/* HAS_* evaluates to true if we may use the feature at runtime. */
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# define HAS_CPU_FEATURE(name) \
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((__get_cpu_features ()->cpuid[index_cpu_##name].reg_##name & (bit_cpu_##name)) != 0)
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CPU_FEATURES_CPU_P (__get_cpu_features (), name)
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# define HAS_ARCH_FEATURE(name) \
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((__get_cpu_features ()->feature[index_arch_##name] & (bit_arch_##name)) != 0)
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CPU_FEATURES_ARCH_P (__get_cpu_features (), name)
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# define index_cpu_CX8 COMMON_CPUID_INDEX_1
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# define index_cpu_CMOV COMMON_CPUID_INDEX_1
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