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aarch64: MTE compatible strchrnul
Introduce an Arm MTE compatible strchrnul implementation. The existing implementation assumes that any access to the pages in which the string resides is safe. This assumption is not true when MTE is enabled. This patch updates the algorithm to ensure that accesses remain within the bounds of an MTE tag (16-byte chunks) and improves overall performance. Benchmarked on Cortex-A72, Cortex-A53, Neoverse N1. Co-authored-by: Wilco Dijkstra <wilco.dijkstra@arm.com>
This commit is contained in:
Andrea Corallo
Szabolcs Nagy
parent
d1f75e9644
commit
f7de454f20
@ -22,109 +22,75 @@
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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* Neon Available.
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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/* Arguments and results. */
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#define srcin x0
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#define chrin w1
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#define result x0
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/* Locals and temporaries. */
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#define src x2
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#define tmp1 x3
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#define wtmp2 w4
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#define tmp3 x5
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#define tmp1 x1
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#define tmp2 x3
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#define tmp2w w3
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#define vrepchr v0
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#define vdata1 v1
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#define vdata2 v2
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#define vhas_nul1 v3
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#define vhas_nul2 v4
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#define vhas_chr1 v5
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#define vhas_chr2 v6
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#define vrepmask v7
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#define vend1 v16
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#define vdata v1
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#define qdata q1
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#define vhas_nul v2
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#define vhas_chr v3
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#define vrepmask v4
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#define vend v5
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#define dend d5
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/* Core algorithm.
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/* Core algorithm:
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For each 32-byte hunk we calculate a 64-bit syndrome value, with
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two bits per byte (LSB is always in bits 0 and 1, for both big
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and little-endian systems). For each tuple, bit 0 is set iff
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the relevant byte matched the requested character or nul. Since the
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bits in the syndrome reflect exactly the order in which things occur
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in the original string a count_trailing_zeros() operation will
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identify exactly which byte is causing the termination. */
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For each 16-byte chunk we calculate a 64-bit syndrome value with four bits
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per byte. For even bytes, bits 0-3 are set if the relevant byte matched the
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requested character or the byte is NUL. Bits 4-7 must be zero. Bits 4-7 are
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set likewise for odd bytes so that adjacent bytes can be merged. Since the
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bits in the syndrome reflect the order in which things occur in the original
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string, counting trailing zeros identifies exactly which byte matched. */
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ENTRY (__strchrnul)
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DELOUSE (0)
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/* Magic constant 0x40100401 to allow us to identify which lane
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matches the termination condition. */
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mov wtmp2, #0x0401
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movk wtmp2, #0x4010, lsl #16
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bic src, srcin, 15
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dup vrepchr.16b, chrin
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bic src, srcin, #31 /* Work with aligned 32-byte hunks. */
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dup vrepmask.4s, wtmp2
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ands tmp1, srcin, #31
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b.eq L(loop)
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/* Input string is not 32-byte aligned. Rather than forcing
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the padding bytes to a safe value, we calculate the syndrome
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for all the bytes, but then mask off those bits of the
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syndrome that are related to the padding. */
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ld1 {vdata1.16b, vdata2.16b}, [src], #32
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neg tmp1, tmp1
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cmeq vhas_nul1.16b, vdata1.16b, #0
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cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
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cmeq vhas_nul2.16b, vdata2.16b, #0
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cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
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orr vhas_chr1.16b, vhas_chr1.16b, vhas_nul1.16b
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orr vhas_chr2.16b, vhas_chr2.16b, vhas_nul2.16b
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and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
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and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
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lsl tmp1, tmp1, #1
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addp vend1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
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mov tmp3, #~0
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addp vend1.16b, vend1.16b, vend1.16b // 128->64
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lsr tmp1, tmp3, tmp1
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mov tmp3, vend1.2d[0]
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bic tmp1, tmp3, tmp1 // Mask padding bits.
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cbnz tmp1, L(tail)
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L(loop):
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ld1 {vdata1.16b, vdata2.16b}, [src], #32
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cmeq vhas_nul1.16b, vdata1.16b, #0
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cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
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cmeq vhas_nul2.16b, vdata2.16b, #0
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cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
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/* Use a fast check for the termination condition. */
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orr vhas_chr1.16b, vhas_nul1.16b, vhas_chr1.16b
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orr vhas_chr2.16b, vhas_nul2.16b, vhas_chr2.16b
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orr vend1.16b, vhas_chr1.16b, vhas_chr2.16b
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addp vend1.2d, vend1.2d, vend1.2d
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mov tmp1, vend1.2d[0]
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ld1 {vdata.16b}, [src]
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mov tmp2w, 0xf00f
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dup vrepmask.8h, tmp2w
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cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
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cmhs vhas_chr.16b, vhas_chr.16b, vdata.16b
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lsl tmp2, srcin, 2
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and vhas_chr.16b, vhas_chr.16b, vrepmask.16b
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addp vend.16b, vhas_chr.16b, vhas_chr.16b /* 128->64 */
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fmov tmp1, dend
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lsr tmp1, tmp1, tmp2 /* Mask padding bits. */
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cbz tmp1, L(loop)
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/* Termination condition found. Now need to establish exactly why
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we terminated. */
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and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
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and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
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addp vend1.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
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addp vend1.16b, vend1.16b, vend1.16b // 128->64
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mov tmp1, vend1.2d[0]
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L(tail):
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/* Count the trailing zeros, by bit reversing... */
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rbit tmp1, tmp1
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/* Re-bias source. */
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sub src, src, #32
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clz tmp1, tmp1 /* ... and counting the leading zeros. */
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/* tmp1 is twice the offset into the fragment. */
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add result, src, tmp1, lsr #1
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clz tmp1, tmp1
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add result, srcin, tmp1, lsr 2
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ret
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.p2align 4
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L(loop):
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ldr qdata, [src, 16]!
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cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
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cmhs vhas_chr.16b, vhas_chr.16b, vdata.16b
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umaxp vend.16b, vhas_chr.16b, vhas_chr.16b
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fmov tmp1, dend
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cbz tmp1, L(loop)
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and vhas_chr.16b, vhas_chr.16b, vrepmask.16b
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addp vend.16b, vhas_chr.16b, vhas_chr.16b /* 128->64 */
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fmov tmp1, dend
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#ifndef __AARCH64EB__
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rbit tmp1, tmp1
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#endif
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clz tmp1, tmp1
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add result, src, tmp1, lsr 2
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ret
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END(__strchrnul)
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