Commit Graph

6 Commits

Author SHA1 Message Date
Maciej W. Rozycki
b72ca61b71 MIPS: Correct the handling of reserved FCSR bits
Reserved bits in the Floating-Point Control and Status Register (FCSR)
should not be implicitly cleared by fedisableexcept or feenableexcept,
there is no reason to.  Among these are the 8 condition codes and one of
the two bits reserved for architecture implementers (bits #22 & #21).

As to the latter, there is no reason to treat any of them as reserved
either, they should be user controllable and settable via __fpu_control
override as the user sees fit.  For example in processors implemented by
MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to
change the treatment of denormalised operands and tiny results: bit #22
is Flush Override (FO) and bit #21 is Flush to Nearest (FN).  They cause
non-IEEE-compliant behaviour, but some programs may have a use for such
modes of operation; the library should not obstruct such use just as it
does not for the architectural Flush to Zero (FS) bit (bit #24).

Therefore the change adjusts the reserved mask accordingly and also
documents the distinction between bits 22:21 and 20:18.
2013-08-22 17:55:17 +01:00
Joseph Myers
5556231db2 Remove trailing whitespace in ports. 2013-06-05 20:26:40 +00:00
Maciej W. Rozycki
43301bd3c2 Add support for building as MIPS16 code. 2013-02-27 23:45:07 +00:00
Joseph Myers
568035b787 Update copyright notices with scripts/update-copyrights. 2013-01-02 19:05:09 +00:00
Joseph Myers
5b5b04d628 Make fma use of Dekker and Knuth algorithms use round-to-nearest (bug 14796). 2012-11-03 19:48:53 +00:00
Joseph Myers
e64ac02c24 Move all files into ports/ subdirectory in preparation for merge with glibc 2012-07-01 13:06:41 +00:00