AuroraMiddleware/glibc
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Author SHA1 Message Date
Adhemerval Zanella
4393fc119c PowerPC: Optimized isinf/isinff for POWER8 
This patch add a optimized isinf/isinff implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.
 2014-02-27 12:58:33 -06:00