4 Commits

Author	SHA1	Message	Date
Joe Ramsay	b0e0a07018	aarch64/fpu: Sync libmvec routines from 2.39 and before with AOR ... This includes a fix for big-endian in AdvSIMD log, some cosmetic changes, and numerous small optimisations mainly around inlining and using indexed variants of MLA intrinsics. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> (cherry picked from commit e302e10213)	2024-04-09 19:58:04 +01:00
Paul Eggert	dff8da6b3e	Update copyright dates with scripts/update-copyrights	2024-01-01 10:53:40 -08:00
Joe Ramsay	cc0d77ba94	aarch64: Add half-width versions of AdvSIMD f32 libmvec routines ... Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>	2023-12-20 08:41:25 +00:00
Joe Ramsay	31aaf6fed9	aarch64: Add vector implementations of exp10 routines ... Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.	2023-10-23 15:00:45 +01:00