3 Commits

Author	SHA1	Message	Date
Paul Eggert	dff8da6b3e	Update copyright dates with scripts/update-copyrights	2024-01-01 10:53:40 -08:00
Joe Ramsay	cc0d77ba94	aarch64: Add half-width versions of AdvSIMD f32 libmvec routines ... Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>	2023-12-20 08:41:25 +00:00
Joe Ramsay	067a34156c	aarch64: Add vector implementations of log10 routines ... A table is also added, which is shared between AdvSIMD and SVE log10.	2023-10-23 15:00:45 +01:00