Commit Graph

10 Commits

Author SHA1 Message Date
Joseph Myers
6d7e8eda9b Update copyright dates with scripts/update-copyrights 2023-01-06 21:14:39 +00:00
Alistair Francis
2e81493fa6 riscv: Remove RV32 floating point functions
We don't need RV32 specific floating point functions, instead make them
generic for RISC-V.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
2022-09-21 14:37:43 -04:00
Alistair Francis
73e9fe43ac riscv: Consolidate the libm-test-ulps
Both RV32 and RV64 should have the same libm-test-ulps, so consolidate
them into a single file.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
2022-09-21 14:37:13 -04:00
Tom Coldrick
d2265570a7 manual: Avoid name collision in libm ULP table [BZ #28956]
The 32-bit and 64-bit variants of RISC-V share the same name - "RISC-V"
- when generating the libm error table for the info pages. This
collision, and the way how the table is generated, mean that the values
in the final table for "RISC-V" may be either for the 32- or 64-bit
variant, with no indication as to which.

As an additional side-effect, this makes the build non-reproducible, as
the error table generated is dependent upon the host filesystem
implementation.

To solve this issue, the libm-test-ulps-name files for both variants
have been modified to include their word size, so as to remove the
collision and provide more accurate information in the table.

An alternative proposed was to merge the two variants' ULP values into a
single file, but this would mean that information about error values is
lost, as the two variants are not identical. Some differences are
considerable, notably the values for the exp() function are large.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
Tested-by: Carlos O'Donell <carlos@redhat.com>
2022-04-11 11:46:10 -04:00
Paul Eggert
581c785bf3 Update copyright dates with scripts/update-copyrights
I used these shell commands:

../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright
(cd ../glibc && git commit -am"[this commit message]")

and then ignored the output, which consisted lines saying "FOO: warning:
copyright statement not found" for each of 7061 files FOO.

I then removed trailing white space from math/tgmath.h,
support/tst-support-open-dev-null-range.c, and
sysdeps/x86_64/multiarch/strlen-vec.S, to work around the following
obscure pre-commit check failure diagnostics from Savannah.  I don't
know why I run into these diagnostics whereas others evidently do not.

remote: *** 912-#endif
remote: *** 913:
remote: *** 914-
remote: *** error: lines with trailing whitespace found
...
remote: *** error: sysdeps/unix/sysv/linux/statx_cp.c: trailing lines
2022-01-01 11:40:24 -08:00
Paul Eggert
2b778ceb40 Update copyright dates with scripts/update-copyrights
I used these shell commands:

../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright
(cd ../glibc && git commit -am"[this commit message]")

and then ignored the output, which consisted lines saying "FOO: warning:
copyright statement not found" for each of 6694 files FOO.
I then removed trailing white space from benchtests/bench-pthread-locks.c
and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this
diagnostic from Savannah:
remote: *** pre-commit check failed ...
remote: *** error: lines with trailing whitespace found
remote: error: hook declined to update refs/heads/master
2021-01-02 12:17:34 -08:00
Zong Li
72dfddeffc RISC-V: Build infrastructure for 32-bit port
This patch lays out the top-level organisation of the RISC-V 32-bit port.
It provides all the Implies files as well as various other fragments of
the build infrastructure.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
2020-08-27 08:17:43 -07:00
Zong Li
2ed993ada6 RISC-V: Fix llrint and llround missing exceptions on RV32
Conversions from a float to a long long on 32-bit RISC-V (RV32) may not
raise the correct exceptions on overflow, it also may raise spurious
"inexact" exceptions on non overflow cases.  This patch fixes the
problem, similarly to the fix for MIPS, ARM and S390.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
2020-08-27 08:17:43 -07:00
Alistair Francis
b2d175cdb7 RISC-V: Add the RV32 libm-test-ulps
Add a libm-test-ulps for RV32, this is the same as the RV64 one.

This dosn't match what is generated by running `make regen-ulps` on RV32
QEMU, but the current in tree RV64 doesn't match that either.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
2020-08-27 08:17:43 -07:00
Zong Li
941a55cf59 RISC-V: Add hard float support for 32-bit CPUs
This patch adds support for hardware floating-point support for the
RV32IF and RV32IFD platforms.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
2020-08-27 08:17:42 -07:00