AuroraMiddleware/glibc
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6 Commits

Author SHA1 Message Date
Xi Ruoyao
0c1d2c277a LoongArch: Use "$fcsr0" instead of "$r0" in _FPU_{GET,SET}CW 
Clang inline-asm parser does not allow using "$r0" in
movfcsr2gr/movgr2fcsr, so everything using _FPU_{GET,SET}CW is now
failing to build with Clang on LoongArch.  As we now requires Binutils
>= 2.41 which supports using "$fcsr0" here, use it instead of "$r0" to
fix the issue.

Link: https://github.com/loongson-community/discussions/issues/53#issuecomment-2081507390
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4142b2368353
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
 2024-05-28 09:17:05 +08:00
Paul Eggert
dff8da6b3e Update copyright dates with scripts/update-copyrights 2024-01-01 10:53:40 -08:00
Joseph Myers
6d7e8eda9b Update copyright dates with scripts/update-copyrights 2023-01-06 21:14:39 +00:00
Xiaolin Tang
5fe2647d31 LoongArch: Hard Float Support for float-point classification functions. 
Use hardware Floating-point instruction fclass.{s/d} to implement
classification functions, i.e finite{f/ }, fpclassify{f/ }, isnan{f/ },
isinf{f/ }, issignaling{f/ }.

       *  sysdeps/loongarch/fpu/s_finite.c: New file.
       *  sysdeps/loongarch/fpu/s_finitef.c: Likewise.
       *  sysdeps/loongarch/fpu/s_fpclassify.c: Likewise.
       *  sysdeps/loongarch/fpu/s_fpclassifyf.c: Likewise.
       *  sysdeps/loongarch/fpu/s_isinf.c: Likewise.
       *  sysdeps/loongarch/fpu/s_isinff.c: Likewise.
       *  sysdeps/loongarch/fpu/s_isnan.c: Likewise.
       *  sysdeps/loongarch/fpu/s_isnanf.c: Likewise.
       *  sysdeps/loongarch/fpu/s_issignaling.c: Likewise.
       *  sysdeps/loongarch/fpu/s_issignalingf.c: Likewise.
       *  sysdeps/loongarch/fpu_control.h: Add _FCLASS_* macro.
 2022-11-14 10:02:41 +08:00
caiyinyu
930993921f LoongArch: Add soft float support. 2022-09-01 09:10:08 +08:00
caiyinyu
c742795dce LoongArch: Generic <math.h> and soft-fp Routines 2022-07-26 12:35:12 -03:00