AuroraMiddleware/glibc
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Author SHA1 Message Date
Zong Li
941a55cf59 RISC-V: Add hard float support for 32-bit CPUs 
This patch adds support for hardware floating-point support for the
RV32IF and RV32IFD platforms.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
 2020-08-27 08:17:42 -07:00