glibc

AuroraMiddleware/glibc

Fork 0

mirror of https://sourceware.org/git/glibc.git synced 2024-11-23 13:30:06 +00:00

Commit Graph

Author	SHA1	Message	Date
Ulrich Drepper	5644ef5461	Fix check for AVX enablement The AVX bit is set if the CPU supports AVX. But this doesn't mean the kernel does. Add checks according to Intel's documentation.	2011-07-20 21:21:03 -04:00
H.J. Lu	4e1e2f4247	Support mixed SSE/AVX audit and check AVX only once. This patch fixes mixed SSE/AVX audit and checks AVX only once in _dl_runtime_profile. When an AVX or SSE register value in pltenter is modified, we have to make sure that the SSE part value is the same in both lr_xmm and lr_vector fields so that pltexit will get the correct value from either lr_xmm or lr_vector fields. AVX-enabled pltenter should update both lr_xmm and lr_vector fields to support stacked AVX/SSE pltenter functions.	2009-08-08 10:54:42 -07:00

Author

SHA1

Message

Date

Ulrich Drepper

5644ef5461

Fix check for AVX enablement

The AVX bit is set if the CPU supports AVX.  But this doesn't mean the
kernel does.  Add checks according to Intel's documentation.

2011-07-20 21:21:03 -04:00

H.J. Lu

4e1e2f4247

Support mixed SSE/AVX audit and check AVX only once.

This patch fixes mixed SSE/AVX audit and checks AVX only once in
_dl_runtime_profile. When an AVX or SSE register value in pltenter is
modified, we have to make sure that the SSE part value is the same in both
lr_xmm and lr_vector fields so that pltexit will get the correct value
from either lr_xmm or lr_vector fields. AVX-enabled pltenter should
update both lr_xmm and lr_vector fields to support stacked AVX/SSE
pltenter functions.

2009-08-08 10:54:42 -07:00

2 Commits