Commit Graph

483 Commits

Author SHA1 Message Date
Mike Frysinger
fe1a83aa1c ia64: ioperm: clean up long dead code
This file has a few #if 0 code paths which cause a build time warning:
ports/sysdeps/unix/sysv/linux/ia64/ioperm.c:66:7: warning:
	variable 'prot' set but not used [-Wunused-but-set-variable]

Rather than add more #if 0 around that variable, just delete the code
altogether.  Not like it's going to ever be implemented.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-12-24 05:34:52 -05:00
Mike Frysinger
41b1792698 ia64: implement sotruss support
Tested with:
	$ cat test.c
	main(){close(0x1024, 2, 3);}
	$ gcc test.c
	$ sotruss -e ./a.out
		a.out -> libc.so.6.1    : __libc_start_main(0x4000000000000950, 0x1, 0x60000fffffb56bc8)
		a.out -> libc.so.6.1    : close(0x1024, 0x2, 0x3)
		a.out -> libc.so.6.1    : close - 0xffffffffffffffff

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-12-24 04:05:46 -05:00
Mike Frysinger
cd702fc455 ia64: link.h: adjust whitespace
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-12-24 04:05:46 -05:00
Marcus Shawcroft
9dbebe1a67 [AArch64] Save and restore q0-q7 on entry to dynamic linker.
[BZ #15128] Ensure all argument passing registers are saved and
restored on entry to dynamic linker.
2013-12-18 12:07:05 +00:00
Marcus Shawcroft
0f197fe5b6 [AArch64] Implement FUTEX_*_REQUEUE_PI 2013-12-17 17:57:34 +00:00
Marcus Shawcroft
e4a110f59e [AArch64] libm-test-ulps regenerated from scratch. 2013-12-17 13:03:01 +00:00
Marcus Shawcroft
653fac831d [AArch64] Back out sqrt() addition to libm-test-ulps. 2013-12-17 12:28:10 +00:00
Marcus Shawcroft
39e1f44ff4 [AArch64] Regenerate libm-test-ulps. 2013-12-11 16:19:34 +00:00
Andreas Schwab
eca60f6ed3 m68k: use math_force_eval in nextafterl 2013-12-10 00:16:12 +01:00
Andreas Schwab
e1c5c75ea2 m68k: add support for PI futexes 2013-12-10 00:16:01 +01:00
Andreas Schwab
2ea2960024 m68k: don't assume PI futexes before 3.10 2013-12-10 00:15:41 +01:00
Richard Henderson
7380e0e469 alpha: Convert <bits/mman.h> to <bits/mman-linux.h> 2013-12-07 06:19:35 +10:00
Joseph Myers
6905a19f7a Update MIPS dl-lookup.c from generic version. 2013-12-03 22:56:05 +00:00
Joseph Myers
3c1c46a64a Fix dbl-64 e_sqrt.c for non-default rounding modes (bug 16271). 2013-11-28 16:50:38 +00:00
Aurelien Jarno
24d8773d06 MIPS: Fix RLIM64_INFINITY constant for O32 and N32 ABIs
Fix the RLIM64_INFINITY constant for O32 and N32 ABIs to match the
kernel one. Change the getrlimit64/setrlimit64 into old compat symbols,
and provide the Linux generic getrlimit64/setrlimit64 functions as
GLIBC_2_19 version.
2013-11-27 17:38:16 +01:00
Aurelien Jarno
9480dfe2a3 MIPS: Add wrappers to get/setrlimit64 to fix RLIM64_INFINITY constant
RLIM64_INFINITY was supposed to be a glibc convention rather than
anything seen by the kernel, but it ended being passed to the kernel
through the prlimit64 syscall.  On O32 and N32 ABIs, we therefore
end-up with different values on the userland and kernel side:

* On the kernel side, the value is defined for all architectures as
  include/uapi/linux/resource.h:

  #define RLIM64_INFINITY           (~0ULL)

* On the GNU libc side, the value is defined in
  ports/sysdeps/unix/sysv/linux/mips/bits/resource.h:

  For the O32 and N32 ABI:
  #  define RLIM64_INFINITY 0x7fffffffffffffffULL

  and for the N64 ABI:
  #  define RLIM64_INFINITY 0xffffffffffffffffUL

This was not a problem until the prlimit64 syscall was wired in the
2.6.36 kernel. Given the GLIBC uses the prlimit64 syscall to implement
getrlimit64 and setrlimit64, pam_limits.so is setting the limits to
a very big value instead of infinity. As a normal user process can
later only decrease the value and not increase it, it will later get
and EPERM error when trying to set the value to infinity with setrlimit.

The GLIBC has this constant for more than 7 years, and as it is defined
in a header file, it means a lot of binaries are in the wild. This patch
fixes that by adding a wrapper to fix the value passed to or received
from the kernel, before or after calling the prlimit64 syscall.
2013-11-27 17:36:51 +01:00
Will Newton
7520ff8c74 aarch64: Enable ifunc support.
Add support for handling the R_AARCH64_IRELATIVE relocation and
STT_GNU_IFUNC symbols to the aarch64 port.

ports/ChangeLog.aarch64:

2013-11-26  Will Newton  <will.newton@linaro.org>

	* sysdeps/aarch64/dl-irel.h: Include ldsodefs.h.
	(ELF_MACHINE_IRELA): Define.  (elf_ifunc_invoke): Pass
	hwcap to ifunc resolver function.  (elf_irela): New function.
	* sysdeps/aarch64/dl-machine.h: Include dl-irel.h.
	(elf_machine_rela) Handle STT_GNU_IFUNC symbols and
	R_AARCH64_IRELATIVE relocations.  (elf_machine_lazy_rel):
	Handle R_AARCH64_IRELATIVE relocations.
2013-11-26 16:18:04 +00:00
Ondřej Bílka
d1d9eaf478 Use __glibc_reserved instead __unused. 2013-11-26 12:32:28 +01:00
Roland McGrath
068dcfd675 ARM: Fix memcpy computed-jump calculations for ARM_ALWAYS_BX case. 2013-11-22 11:39:20 -08:00
Guy Martin
daf75146de Don't use broken DL_AUTO_FUNCTION_ADDRESS()
On hppa and ia64, the macro DL_AUTO_FUNCTION_ADDRESS() uses the
variable fptr[2] in it's own scope.

The content of fptr[] is thus undefined right after the macro exits.
Newer gcc's (>= 4.7) reuse the stack space of this variable triggering
a segmentation fault in dl-init.c:69.

To fix this we rewrite the macros to make the call directly to init
and fini without needing to pass back a constructed function pointer.
2013-11-21 15:52:31 -05:00
Chung-Lin Tang
7cf8ac4c31 linux-generic: fix alignment of struct stat/statfs for nios2
The hard alignment of 8 was appropriate for most platforms for
which 8-byte values are 8-byte aligned, but this is not true
for the nios2 platform, so only align to the alignment of the
8-byte type on the platform.

Remove the explicit alignment of struct statfs as it's redundant.
2013-11-20 16:12:18 -05:00
Richard Henderson
027e32bd42 alpha: Fix signal thunk unwind info 2013-11-16 06:34:39 +10:00
Mike Frysinger
cb8a6dbd17 rename configure.in to configure.ac
Autoconf has been deprecating configure.in for quite a long time.
Rename all our configure.in and preconfigure.in files to .ac.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-10-30 17:32:08 +10:00
Yuri Chornoivan
5560275828 Fix typos. 2013-10-12 14:47:50 +02:00
Andreas Schwab
7d0c5ed0fe Fix typo in last change 2013-10-08 21:25:12 +02:00
Andreas Schwab
ed4c993944 m68k: use PIC for Scrt1.o 2013-10-08 21:02:23 +02:00
Joseph Myers
29d73d867e Move powerpc ports pieces to libc. 2013-10-04 16:02:33 +00:00
Joseph Myers
cd78f7e767 e500 port: getcontext / setcontext / swapcontext. 2013-10-04 15:55:15 +00:00
Will Newton
41bc5e0935 ARM: Allow building __sigsetjmp as Thumb.
Convert __sigsetjmp code to allow building as Thumb.

ports/ChangeLog.arm:

2013-10-04  Will Newton  <will.newton@linaro.org>

	* sysdeps/arm/setjmp.S (NO_THUMB): Remove define.
	(__sigsetjmp): Use Thumb supported instructions.
2013-10-04 10:54:58 +01:00
Will Newton
6d9b9a67af ARM: Allow building __longjmp as Thumb.
Convert __longjmp code to allow building as Thumb.

ports/ChangeLog.arm:

2013-10-04  Will Newton  <will.newton@linaro.org>

	* sysdeps/arm/__longjmp.S (NO_THUMB): Remove define.
	(__longjmp): Use Thumb supported instructions.
	* sysdeps/unix/sysv/linux/arm/____longjmp_chk.S (NO_THUMB):
	Remove define.
2013-10-04 10:53:43 +01:00
Alan Modra
1b6adf888d PowerPC floating point little-endian [1 of 15]
http://sourceware.org/ml/libc-alpha/2013-08/msg00081.html

This is the first of a series of patches to ban ieee854_long_double
and the ieee854_long_double macros when using IBM long double.  union
ieee854_long_double just isn't correct for IBM long double, especially
when little-endian, and pretending it is OK has allowed a number of
bugs to remain undetected in sysdeps/ieee754/ldbl-128ibm/.

This changes the few places in generic code that use it.

	* stdio-common/printf_size.c (__printf_size): Don't use
	union ieee854_long_double in fpnum union.
	* stdio-common/printf_fphex.c (__printf_fphex): Likewise.  Use
	signbit macro to retrieve sign from long double.
	* stdio-common/printf_fp.c (___printf_fp): Use signbit macro to
	retrieve sign from long double.
	* sysdeps/ieee754/ldbl-128ibm/printf_fphex.c: Adjust for fpnum change.
	* sysdeps/ieee754/ldbl-128/printf_fphex.c: Likewise.
	* sysdeps/ieee754/ldbl-96/printf_fphex.c: Likewise.
	* sysdeps/x86_64/fpu/printf_fphex.c: Likewise.
	* math/test-misc.c (main): Don't use union ieee854_long_double.
ports/
	* sysdeps/ia64/fpu/printf_fphex.c: Adjust for fpnum change.
2013-10-04 10:31:41 +09:30
Steve Ellcey
bc543b02c7 2013-09-26 Steve Ellcey <sellcey@mips.com>
[BZ #15632]
	* sysdeps/mips/mips32/fpu/e_sqrt.c: New.
	* sysdeps/mips/mips32/fpu/e_sqrtf.c: New.
	* sysdeps/mips/mips64/n32/fpu/e_sqrt.c: New.
	* sysdeps/mips/mips64/n32/fpu/e_sqrtf.c: New.
	* sysdeps/mips/mips64/n64/fpu/e_sqrt.c: New.
	* sysdeps/mips/mips64/n64/fpu/e_sqrtf.c: New.
2013-10-03 12:56:34 -07:00
Will Newton
b7f2d27dbd ARM: Add pointer encryption support.
Add support for pointer encryption in glibc internal structures in C
and assembler code. Pointer encryption is a glibc security feature
described here:

https://sourceware.org/glibc/wiki/PointerEncryption

The ARM implementation uses global variables instead of thread pointer
relative accesses to get the value of the pointer encryption guard
because accessing the thread pointer can be very expensive on older
ARM cores.

ports/ChangeLog.arm:

2013-10-03  Will Newton  <will.newton@linaro.org>

	* sysdeps/arm/__longjmp.S (__longjmp): Demangle fp, sp
	and lr when restoring register values.
	* sysdeps/arm/include/bits/setjmp.h (JMP_BUF_REGLIST): Remove
	sp and lr from list and replace fp with a4.
	* sysdeps/arm/jmpbuf-unwind.h (_jmpbuf_sp): New function.
	(_JMPBUF_UNWINDS_ADJ): Call _jmpbuf_sp.
	* sysdeps/arm/setjmp.S (__sigsetjmp): Mangle fp, sp and lr
	before storing register values.
	* sysdeps/arm/sysdep.h (LDST_GLOBAL): New macro.
	* sysdeps/unix/sysv/linux/arm/sysdep.h (PTR_MANGLE): New macro.
	(PTR_DEMANGLE): Likewise. (PTR_MANGLE2): Likewise.
	(PTR_DEMANGLE2): Likewise.
2013-10-03 11:35:50 +01:00
Richard Henderson
b8123ef5b1 alpha: Improve conditions under which PTR_MANGLE is defined
After 0b1f8e3564, we now have
a __pointer_chk_guard_local for the static libc.
2013-10-01 12:27:02 -07:00
Andrew Pinski
995a05b173 [AArch64] Fix BE access to errno. 2013-09-30 10:58:26 +01:00
Marcus Shawcroft
8f5a90c270 [AArch64] Support __mcount profiling. 2013-09-24 13:03:02 +01:00
Marcus Shawcroft
cfa4df9500 [AArch64] Adding sigcontextinfo.h 2013-09-24 12:59:06 +01:00
Will Newton
82c93a0ffe ports/sysdeps/arm/nptl/tls.h: Remove TLS_INIT_TP_EXPENSIVE.
This define was removed from the rest of the tree eight years ago.

ports/ChangeLog.arm:

2013-09-24  Will Newton  <will.newton@linaro.org>

	* ports/sysdeps/arm/nptl/tls.h (TLS_INIT_TP_EXPENSIVE): Remove
	macro.
2013-09-24 09:29:04 +01:00
Steve Ellcey
c79fb0ed65 2013-09-23 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/math_private.h (libc_feholdexcept_mips): New function.
	(libc_feholdexcept): New macro.
	(libc_feholdexceptf): New macro.
	(libc_feholdexceptl): New macro.
	(libc_fesetround_mips): New function.
	(libc_fesetround): New macro.
	(libc_fesetroundf): New macro.
	(libc_fesetroundl): New macro.
	(libc_feholdexcept_setround_mips): New function.
	(libc_feholdexcept_setround): New macro.
	(libc_feholdexcept_setroundf): New macro.
	(libc_feholdexcept_setroundl): New macro.
	(libc_fesetenv_mips): New function.
	(libc_fesetenv): New macro.
	(libc_fesetenvf): New macro.
	(libc_fesetenvl): New macro.
	(libc_feupdateenv_mips): New function.
	(libc_feupdateenv): New macro.
	(libc_feupdateenvf): New macro.
	(libc_feupdateenvl): New macro.
2013-09-23 09:58:30 -07:00
Maciej W. Rozycki
d93fa6592b MIPS: bits/atomic.h: Fix comment typo 2013-09-23 17:45:34 +01:00
Steve Ellcey
6b9a5fe450 2013-09-23 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/fpu/fegetround.c (fegetround): Use _FPU_RC_MASK.
	* sysdeps/mips/fpu/fesetround.c (fesetround): Use _FPU_RC_MASK.
2013-09-23 09:39:32 -07:00
Steve Ellcey
5b04bb073c 2013-09-19 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/fpu_control.h (_FPU_RC_MASK): New.
2013-09-23 09:34:15 -07:00
Steve Ellcey
2487f2e6a5 2013-09-23 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/fpu_control.h (comments): Add capitalization and
	periods to match GNU standard.
2013-09-23 09:29:58 -07:00
Carlos O'Donell
c61b4d41c9 BZ #15754: CVE-2013-4788
The pointer guard used for pointer mangling was not initialized for
static applications resulting in the security feature being disabled.
The pointer guard is now correctly initialized to a random value for
static applications. Existing static applications need to be
recompiled to take advantage of the fix.

The test tst-ptrguard1-static and tst-ptrguard1 add regression
coverage to ensure the pointer guards are sufficiently random
and initialized to a default value.
2013-09-23 00:52:09 -04:00
Andreas Schwab
5bb43a4319 Make __ffs hidden 2013-09-20 21:25:31 +02:00
Steve Ellcey
4f864b3500 2013-09-20 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/memset.S: Change prefetching and add loop unrolling.
	* sysdeps/mips/mips64/memset.S: Remove.
2013-09-20 10:29:51 -07:00
Steve Ellcey
79440ec78c 2013-09-20 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/memset.S: Change prefetching and add loop unrolling.
	* sysdeps/mips/mips64/memset.S: Remove.
2013-09-20 10:29:25 -07:00
Maxim Kuvyrkov
d70d6205fa Improve atomic locking for ARM.
[BZ #15640]
	* sysdeps/arm/bits/atomic.h (atomic_exchange_acq, atomic_exchange_rel)
	(atomic_compare_and_exchange_bool_acq)
	(atomic_compare_and_exchange_val_acq)
	(atomic_compare_and_exchange_bool_rel)
	(atomic_compare_and_exchange_val_rel): Use __atomic_exchange_n and
	__atomic_compare_exchange_n builtins when GCC supports them.
2013-09-19 18:50:17 +12:00
Maciej W. Rozycki
9c21573c02 MIPS: IEEE 754-2008 NaN encoding support
It has been a long practice for software using IEEE 754 floating-point
arithmetic run on MIPS processors to use an encoding of Not-a-Number
(NaN) data different to one used by software run on other processors.
And as of IEEE 754-2008 revision [1] this encoding does not follow one
recommended in the standard, as specified in section 6.2.1, where it
is stated that quiet NaNs should have the first bit (d1) of their
significand set to 1 while signalling NaNs should have that bit set to
0, but MIPS software interprets the two bits in the opposite manner.

As from revision 3.50 [2][3] the MIPS Architecture provides for
processors that support the IEEE 754-2008 preferred NaN encoding format.
As the two formats (further referred to as "legacy NaN" and "2008 NaN")
are incompatible to each other, tools have to provide support for the
two formats to help people avoid using incompatible binary modules.

The change is comprised of two functional groups of features, both of
which are required for correct support.

1. Dynamic linker support.

   To enforce the NaN encoding requirement in dynamic linking a new ELF
   file header flag has been defined.  This flag is set for 2008-NaN
   shared modules and executables and clear for legacy-NaN ones.  The
   dynamic linker silently ignores any incompatible modules it
   encounters in dependency processing.

   To avoid unnecessary processing of incompatible modules in the
   presence of a shared module cache, a set of new cache flags has been
   defined to mark 2008-NaN modules for the three ABIs supported.
   Changes to sysdeps/unix/sysv/linux/mips/readelflib.c have been made
   following an earlier code quality suggestion made here:

   http://sourceware.org/ml/libc-ports/2009-03/msg00036.html

   and are therefore a little bit more extensive than the minimum
   required.

   Finally a new name has been defined for the dynamic linker so that
   2008-NaN and legacy-NaN binaries can coexist on a single system that
   supports dual-mode operation and that a legacy dynamic linker that
   does not support verifying the 2008-NaN ELF file header flag is not
   chosen to interpret a 2008-NaN binary by accident.

2. Floating environment support.

   IEEE 754-2008 features are controlled in the Floating-Point Control
   and Status (FCSR) register and updates are needed to floating
   environment support so that the 2008-NaN flag is set correctly and
   the kernel default, inferred from the 2008-NaN ELF file header flag
   at the time an executable is loaded, respected.

As the NaN encoding format is a property of GCC code generation that is
both a user-selected GCC configuration default and can be overridden
with GCC options, code that needs to know what NaN encoding standard it
has been configured for checks for the __mips_nan2008 macro that is
defined internally by GCC whenever the 2008-NaN mode has been selected.
This mode is determined at the glibc configuration time and therefore a
few consistency checks have been added to catch cases where compilation
flags have been overridden by the user.

The 2008 NaN set of features relies on kernel support as the in-kernel
floating-point emulator needs to be aware of the NaN encoding used even
on hard-float processors and configure the FPU context according to the
value of the 2008 NaN ELF file header flag of the executable being
started.  As at this time work on kernel support is still in progress
and the relevant changes have not made their way yet to linux.org master
repository.

Therefore the minimum version supported has been artificially set to
10.0.0 so that 2008-NaN code is not accidentally run on a Linux kernel
that does not suppport it.  It is anticipated that the version is
adjusted later on to the actual initial linux.org kernel version to
support this feature.  Legacy NaN encoding support is unaffected, older
kernel versions remain supported.

[1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer
    Society, IEEE Std 754-2008, 29 August 2008

[2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
    MD00082, Revision 3.50, September 20, 2012

[3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
    MD00083, Revision 3.50, September 20, 2012
2013-09-18 21:33:50 +01:00
Will Newton
cd90698b54 ARM: Improve armv7 memcpy performance.
Only enter the aligned copy loop with buffers that can be 8-byte
aligned. This improves performance slightly on Cortex-A9 and
Cortex-A15 cores for large copies with buffers that are 4-byte
aligned but not 8-byte aligned.

ports/ChangeLog.arm:

2013-09-16  Will Newton  <will.newton@linaro.org>

	* sysdeps/arm/armv7/multiarch/memcpy_impl.S: Tighten check
	on entry to aligned copy loop to improve performance.
2013-09-16 17:55:28 +01:00