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8ecb477ea1
Remove memset-reg.h by moving register definitions into the memset implementations. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
177 lines
4.2 KiB
ArmAsm
177 lines
4.2 KiB
ArmAsm
/* Optimized memset for Fujitsu A64FX processor.
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Copyright (C) 2021-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* Assumptions:
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*
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* ARMv8.2-a, AArch64, unaligned accesses, sve
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*
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*/
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#define L1_SIZE (64*1024) // L1 64KB
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#define L2_SIZE (8*1024*1024) // L2 8MB
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#define CACHE_LINE_SIZE 256
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#define PF_DIST_L1 (CACHE_LINE_SIZE * 16) // Prefetch distance L1
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#define vector_length x9
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#if HAVE_AARCH64_SVE_ASM
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.arch armv8.2-a+sve
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#define dstin x0
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define tmp1 x5
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#define tmp2 x6
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.macro st1b_unroll first=0, last=7
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st1b z0.b, p0, [dst, \first, mul vl]
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.if \last-\first
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st1b_unroll "(\first+1)", \last
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.endif
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.endm
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#undef BTI_C
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#define BTI_C
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ENTRY (__memset_a64fx)
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PTR_ARG (0)
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SIZE_ARG (2)
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cntb vector_length
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dup z0.b, valw
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whilelo p0.b, vector_length, count
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b.last 1f
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whilelo p1.b, xzr, count
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st1b z0.b, p1, [dstin, 0, mul vl]
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st1b z0.b, p0, [dstin, 1, mul vl]
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ret
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// count >= vector_length * 2
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1: cmp count, vector_length, lsl 2
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add dstend, dstin, count
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b.hi 1f
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st1b z0.b, p0, [dstin, 0, mul vl]
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st1b z0.b, p0, [dstin, 1, mul vl]
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st1b z0.b, p0, [dstend, -2, mul vl]
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st1b z0.b, p0, [dstend, -1, mul vl]
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ret
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// count > vector_length * 4
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1: lsl tmp1, vector_length, 3
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cmp count, tmp1
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b.hi L(vl_agnostic)
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st1b z0.b, p0, [dstin, 0, mul vl]
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st1b z0.b, p0, [dstin, 1, mul vl]
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st1b z0.b, p0, [dstin, 2, mul vl]
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st1b z0.b, p0, [dstin, 3, mul vl]
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st1b z0.b, p0, [dstend, -4, mul vl]
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st1b z0.b, p0, [dstend, -3, mul vl]
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st1b z0.b, p0, [dstend, -2, mul vl]
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st1b z0.b, p0, [dstend, -1, mul vl]
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ret
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.p2align 4
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L(vl_agnostic): // VL Agnostic
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mov dst, dstin
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cmp count, L1_SIZE
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b.hi L(L1_prefetch)
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// count >= 8 * vector_length
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L(unroll8):
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sub count, count, tmp1
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.p2align 4
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// The 2 instructions at the beginning of the following loop,
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// cmp and branch, are a workaround so as not to degrade at
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// the peak performance 16KB.
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// It is found heuristically and the branch condition, b.ne,
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// is chosen intentionally never to jump.
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1: cmp xzr, xzr
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b.ne 1b
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st1b_unroll 0, 7
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add dst, dst, tmp1
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subs count, count, tmp1
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b.hi 1b
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add count, count, tmp1
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L(last):
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cmp count, vector_length, lsl 1
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b.ls 2f
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add tmp2, vector_length, vector_length, lsl 2
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cmp count, tmp2
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b.ls 5f
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st1b z0.b, p0, [dstend, -8, mul vl]
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st1b z0.b, p0, [dstend, -7, mul vl]
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st1b z0.b, p0, [dstend, -6, mul vl]
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5: st1b z0.b, p0, [dstend, -5, mul vl]
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st1b z0.b, p0, [dstend, -4, mul vl]
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st1b z0.b, p0, [dstend, -3, mul vl]
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2: st1b z0.b, p0, [dstend, -2, mul vl]
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st1b z0.b, p0, [dstend, -1, mul vl]
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ret
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// count >= L1_SIZE
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.p2align 3
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L(L1_prefetch):
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cmp count, L2_SIZE
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b.hs L(L2)
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cmp vector_length, 64
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b.ne L(unroll8)
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1: st1b_unroll 0, 3
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prfm pstl1keep, [dst, PF_DIST_L1]
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st1b_unroll 4, 7
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prfm pstl1keep, [dst, PF_DIST_L1 + CACHE_LINE_SIZE]
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add dst, dst, CACHE_LINE_SIZE * 2
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sub count, count, CACHE_LINE_SIZE * 2
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cmp count, PF_DIST_L1
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b.hs 1b
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b L(unroll8)
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// count >= L2_SIZE
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.p2align 3
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L(L2):
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tst valw, 255
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b.ne L(unroll8)
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// align dst to CACHE_LINE_SIZE byte boundary
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and tmp2, dst, CACHE_LINE_SIZE - 1
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st1b z0.b, p0, [dst, 0, mul vl]
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st1b z0.b, p0, [dst, 1, mul vl]
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st1b z0.b, p0, [dst, 2, mul vl]
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st1b z0.b, p0, [dst, 3, mul vl]
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sub dst, dst, tmp2
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add count, count, tmp2
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// clear cachelines using DC ZVA
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sub count, count, CACHE_LINE_SIZE * 2
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.p2align 4
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1: add dst, dst, CACHE_LINE_SIZE
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dc zva, dst
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subs count, count, CACHE_LINE_SIZE
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b.hi 1b
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add count, count, CACHE_LINE_SIZE
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b L(last)
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END (__memset_a64fx)
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#endif /* HAVE_AARCH64_SVE_ASM */
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