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108 lines
4.2 KiB
C
108 lines
4.2 KiB
C
/* Raise given exceptions.
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Copyright (C) 2004-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <fpu_control.h>
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#include <fenv.h>
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#include <float.h>
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#include <arm-features.h>
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int
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__feraiseexcept (int excepts)
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{
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/* Fail if a VFP unit isn't present unless nothing needs to be done. */
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if (!ARM_HAVE_VFP)
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return (excepts != 0);
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else
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{
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fpu_control_t fpscr;
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const float fp_zero = 0.0, fp_one = 1.0, fp_max = FLT_MAX,
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fp_min = FLT_MIN, fp_1e32 = 1.0e32f, fp_two = 2.0,
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fp_three = 3.0;
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/* Raise exceptions represented by EXPECTS. But we must raise only
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one signal at a time. It is important that if the overflow/underflow
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exception and the inexact exception are given at the same time,
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the overflow/underflow exception follows the inexact exception. After
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each exception we read from the fpscr, to force the exception to be
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raised immediately. */
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/* There are additional complications because this file may be compiled
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without VFP support enabled, and we also can't assume that the
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assembler has VFP instructions enabled. To get around this we use the
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generic coprocessor mnemonics and avoid asking GCC to put float values
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in VFP registers. */
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/* First: invalid exception. */
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if (FE_INVALID & excepts)
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__asm__ __volatile__ (
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"ldc p10, cr0, %1\n\t" /* flds s0, %1 */
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"cdp p10, 8, cr0, cr0, cr0, 0\n\t" /* fdivs s0, s0, s0 */
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"mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
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: "m" (fp_zero)
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: "s0");
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/* Next: division by zero. */
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if (FE_DIVBYZERO & excepts)
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__asm__ __volatile__ (
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"ldc p10, cr0, %1\n\t" /* flds s0, %1 */
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"ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
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"cdp p10, 8, cr0, cr0, cr0, 1\n\t" /* fdivs s0, s0, s1 */
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"mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
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: "m" (fp_one), "m" (fp_zero)
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: "s0", "s1");
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/* Next: overflow. */
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if (FE_OVERFLOW & excepts)
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/* There's no way to raise overflow without also raising inexact. */
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__asm__ __volatile__ (
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"ldc p10, cr0, %1\n\t" /* flds s0, %1 */
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"ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
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"cdp p10, 3, cr0, cr0, cr0, 1\n\t" /* fadds s0, s0, s1 */
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"mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
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: "m" (fp_max), "m" (fp_1e32)
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: "s0", "s1");
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/* Next: underflow. */
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if (FE_UNDERFLOW & excepts)
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__asm__ __volatile__ (
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"ldc p10, cr0, %1\n\t" /* flds s0, %1 */
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"ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
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"cdp p10, 8, cr0, cr0, cr0, 1\n\t" /* fdivs s0, s0, s1 */
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"mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
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: "m" (fp_min), "m" (fp_three)
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: "s0", "s1");
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/* Last: inexact. */
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if (FE_INEXACT & excepts)
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__asm__ __volatile__ (
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"ldc p10, cr0, %1\n\t" /* flds s0, %1 */
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"ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
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"cdp p10, 8, cr0, cr0, cr0, 1\n\t" /* fdivs s0, s0, s1 */
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"mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
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: "m" (fp_two), "m" (fp_three)
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: "s0", "s1");
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/* Success. */
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return 0;
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}
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}
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libm_hidden_def (__feraiseexcept)
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weak_alias (__feraiseexcept, feraiseexcept)
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libm_hidden_weak (feraiseexcept)
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