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c776fa113d
This patch contains code that needs to directly know about the RISC-V ABI, which is specified in a work-in-progress psABI document: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md This is meant to contain all the RISC-V code that needs to explicitly name registers or manage in-memory structure layout. This does not contain any of the Linux-specific code. 2018-01-29 Palmer Dabbelt <palmer@sifive.com> * sysdeps/riscv/__longjmp.S: New file. * sysdeps/riscv/backtrace.c: Likewise. * sysdeps/riscv/bits/endian.h: Likewise. * sysdeps/riscv/bits/setjmp.h: Likewise. * sysdeps/riscv/bits/wordsize.h: Likewise. * sysdeps/riscv/bsd-_setjmp.c: Likewise. * sysdeps/riscv/bsd-setjmp.c: Likewise. * sysdeps/riscv/dl-trampoline.S: Likewise. * sysdeps/riscv/gccframe.h: Likewise. * sysdeps/riscv/jmpbuf-offsets.h: Likewise. * sysdeps/riscv/jmpbuf-unwind.h: Likewise. * sysdeps/riscv/machine-gmon.h: Likewise. * sysdeps/riscv/memusage.h: Likewise. * sysdeps/riscv/setjmp.S: Likewise. * sysdeps/riscv/sys/asm.h: Likewise. * sysdeps/riscv/tls-macros.h: Likewise.
58 lines
1.7 KiB
ArmAsm
58 lines
1.7 KiB
ArmAsm
/* longjmp, RISC-V version.
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Copyright (C) 1996-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <sys/asm.h>
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ENTRY (__longjmp)
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REG_L ra, 0*SZREG(a0)
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REG_L s0, 1*SZREG(a0)
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REG_L s1, 2*SZREG(a0)
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REG_L s2, 3*SZREG(a0)
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REG_L s3, 4*SZREG(a0)
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REG_L s4, 5*SZREG(a0)
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REG_L s5, 6*SZREG(a0)
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REG_L s6, 7*SZREG(a0)
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REG_L s7, 8*SZREG(a0)
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REG_L s8, 9*SZREG(a0)
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REG_L s9, 10*SZREG(a0)
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REG_L s10,11*SZREG(a0)
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REG_L s11,12*SZREG(a0)
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REG_L sp, 13*SZREG(a0)
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#ifndef __riscv_float_abi_soft
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FREG_L fs0, 14*SZREG+ 0*SZFREG(a0)
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FREG_L fs1, 14*SZREG+ 1*SZFREG(a0)
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FREG_L fs2, 14*SZREG+ 2*SZFREG(a0)
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FREG_L fs3, 14*SZREG+ 3*SZFREG(a0)
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FREG_L fs4, 14*SZREG+ 4*SZFREG(a0)
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FREG_L fs5, 14*SZREG+ 5*SZFREG(a0)
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FREG_L fs6, 14*SZREG+ 6*SZFREG(a0)
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FREG_L fs7, 14*SZREG+ 7*SZFREG(a0)
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FREG_L fs8, 14*SZREG+ 8*SZFREG(a0)
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FREG_L fs9, 14*SZREG+ 9*SZFREG(a0)
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FREG_L fs10,14*SZREG+10*SZFREG(a0)
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FREG_L fs11,14*SZREG+11*SZFREG(a0)
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#endif
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seqz a0, a1
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add a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1
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ret
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END (__longjmp)
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