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04d5556197
* sysdeps/mips/sys/asm.h (PTR_ADDU): Use addu on mips32r6/mips64r6. (PTR_ADDIU): Use addiu for mips32r6/mips64r6. (PTR_SUBU): Use subu for mips32r6/mips64r6. (PTR_SUBIU): Use subu for mips32r6/mips64r6 (subiu does not exist). * sysdeps/mips/machine-gmon.h (PTR_ADDU_STRING) Use addu for mips32r6/mips64r6. (PTR_SUBU_STRING) Use subu for mips32r6/mips64r6.
499 lines
12 KiB
C
499 lines
12 KiB
C
/* Copyright (C) 1997-2014 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ralf Baechle <ralf@gnu.org>.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _SYS_ASM_H
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#define _SYS_ASM_H
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#include <sgidefs.h>
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#ifndef CAT
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# define __CAT(str1,str2) str1##str2
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# define CAT(str1,str2) __CAT(str1,str2)
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#endif
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/* Redefined as nonempty in the internal header. */
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#define __mips_cfi_startproc /* Empty. */
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#define __mips_cfi_endproc /* Empty. */
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/*
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* Macros to handle different pointer/register sizes for 32/64-bit code
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*
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* 64 bit address space isn't used yet, so we may use the R3000 32 bit
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* defines for now.
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*/
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#if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32
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# define PTR .word
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# define PTRSIZE 4
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# define PTRLOG 2
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#elif _MIPS_SIM == _ABI64
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# define PTR .dword
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# define PTRSIZE 8
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# define PTRLOG 3
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#endif
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/*
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* PIC specific declarations
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*/
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#if _MIPS_SIM == _ABIO32
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# ifdef __PIC__
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# define CPRESTORE(register) \
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.cprestore register
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# define CPLOAD(register) \
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.cpload register
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# else
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# define CPRESTORE(register)
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# define CPLOAD(register)
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# endif
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# define CPADD(register) \
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.cpadd register
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/*
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* Set gp when at 1st instruction
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*/
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# define SETUP_GP \
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.set noreorder; \
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.cpload $25; \
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.set reorder
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/* Set gp when not at 1st instruction */
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# define SETUP_GPX(r) \
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.set noreorder; \
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move r, $31; /* Save old ra. */ \
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bal 10f; /* Find addr of cpload. */ \
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nop; \
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10: \
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.cpload $31; \
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move $31, r; \
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.set reorder
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# define SETUP_GPX_L(r, l) \
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.set noreorder; \
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move r, $31; /* Save old ra. */ \
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bal l; /* Find addr of cpload. */ \
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nop; \
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l: \
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.cpload $31; \
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move $31, r; \
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.set reorder
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# define SAVE_GP(x) \
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.cprestore x /* Save gp trigger t9/jalr conversion. */
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# define SETUP_GP64(a, b)
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# define SETUP_GPX64(a, b)
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# define SETUP_GPX64_L(cp_reg, ra_save, l)
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# define RESTORE_GP64
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# define USE_ALT_CP(a)
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#else /* _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32 */
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/*
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* For callee-saved gp calling convention:
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*/
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# define SETUP_GP
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# define SETUP_GPX(r)
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# define SETUP_GPX_L(r, l)
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# define SAVE_GP(x)
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# define SETUP_GP64(gpoffset, proc) \
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.cpsetup $25, gpoffset, proc
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# define SETUP_GPX64(cp_reg, ra_save) \
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move ra_save, $31; /* Save old ra. */ \
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.set noreorder; \
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bal 10f; /* Find addr of .cpsetup. */ \
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nop; \
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10: \
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.set reorder; \
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.cpsetup $31, cp_reg, 10b; \
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move $31, ra_save
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# define SETUP_GPX64_L(cp_reg, ra_save, l) \
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move ra_save, $31; /* Save old ra. */ \
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.set noreorder; \
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bal l; /* Find addr of .cpsetup. */ \
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nop; \
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l: \
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.set reorder; \
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.cpsetup $31, cp_reg, l; \
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move $31, ra_save
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# define RESTORE_GP64 \
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.cpreturn
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/* Use alternate register for context pointer. */
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# define USE_ALT_CP(reg) \
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.cplocal reg
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#endif /* _MIPS_SIM != _ABIO32 */
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/*
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* Stack Frame Definitions
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*/
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#if _MIPS_SIM == _ABIO32
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# define NARGSAVE 4 /* Space for 4 argument registers must be allocated. */
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#endif
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#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32
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# define NARGSAVE 0 /* No caller responsibilities. */
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#endif
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/*
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* LEAF - declare leaf routine
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*/
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#define LEAF(symbol) \
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.globl symbol; \
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.align 2; \
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.type symbol,@function; \
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.ent symbol,0; \
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symbol: .frame sp,0,ra; \
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__mips_cfi_startproc
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/*
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* NESTED - declare nested routine entry point
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*/
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#define NESTED(symbol, framesize, rpc) \
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.globl symbol; \
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.align 2; \
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.type symbol,@function; \
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.ent symbol,0; \
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symbol: .frame sp, framesize, rpc; \
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__mips_cfi_startproc
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/*
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* END - mark end of function
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*/
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#ifndef END
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# define END(function) \
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__mips_cfi_endproc; \
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.end function; \
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.size function,.-function
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#endif
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/*
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* EXPORT - export definition of symbol
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*/
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#define EXPORT(symbol) \
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.globl symbol; \
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symbol: __mips_cfi_startproc
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/*
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* ABS - export absolute symbol
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*/
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#define ABS(symbol,value) \
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.globl symbol; \
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symbol = value
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#define PANIC(msg) \
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.set push; \
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.set reorder; \
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la a0,8f; \
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jal panic; \
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9: b 9b; \
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.set pop; \
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TEXT(msg)
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/*
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* Print formated string
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*/
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#define PRINT(string) \
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.set push; \
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.set reorder; \
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la a0,8f; \
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jal printk; \
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.set pop; \
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TEXT(string)
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#define TEXT(msg) \
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.data; \
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8: .asciiz msg; \
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.previous;
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/*
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* Build text tables
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*/
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#define TTABLE(string) \
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.text; \
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.word 1f; \
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.previous; \
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.data; \
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1: .asciz string; \
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.previous
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/*
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* MIPS IV pref instruction.
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* Use with .set noreorder only!
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*
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* MIPS IV implementations are free to treat this as a nop. The R5000
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* is one of them. So we should have an option not to use this instruction.
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*/
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#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
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(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
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# define PREF(hint,addr) \
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pref hint,addr
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# define PREFX(hint,addr) \
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prefx hint,addr
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#else
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# define PREF(hint,addr)
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# define PREFX(hint,addr)
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#endif
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/*
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* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
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*/
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#if _MIPS_ISA == _MIPS_ISA_MIPS1
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# define MOVN(rd,rs,rt) \
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.set push; \
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.set reorder; \
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beqz rt,9f; \
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move rd,rs; \
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.set pop; \
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9:
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# define MOVZ(rd,rs,rt) \
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.set push; \
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.set reorder; \
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bnez rt,9f; \
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move rd,rt; \
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.set pop; \
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9:
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#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
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#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
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# define MOVN(rd,rs,rt) \
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.set push; \
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.set noreorder; \
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bnezl rt,9f; \
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move rd,rs; \
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.set pop; \
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9:
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# define MOVZ(rd,rs,rt) \
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.set push; \
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.set noreorder; \
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beqzl rt,9f; \
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movz rd,rs; \
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.set pop; \
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9:
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#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
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#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
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(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
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# define MOVN(rd,rs,rt) \
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movn rd,rs,rt
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# define MOVZ(rd,rs,rt) \
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movz rd,rs,rt
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#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
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/*
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* Stack alignment
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*/
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#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32
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# define ALSZ 15
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# define ALMASK ~15
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#else
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# define ALSZ 7
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# define ALMASK ~7
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#endif
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/*
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* Size of a register
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*/
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#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32
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# define SZREG 8
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#else
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# define SZREG 4
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#endif
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/*
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* Use the following macros in assemblercode to load/store registers,
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* pointers etc.
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*/
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#if (SZREG == 4)
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# define REG_S sw
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# define REG_L lw
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#else
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# define REG_S sd
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# define REG_L ld
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#endif
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/*
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* How to add/sub/load/store/shift C int variables.
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*/
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#if (_MIPS_SZINT == 32)
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# define INT_ADD add
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# define INT_ADDI addi
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# define INT_ADDU addu
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# define INT_ADDIU addiu
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# define INT_SUB sub
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# define INT_SUBI subi
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# define INT_SUBU subu
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# define INT_SUBIU subu
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# define INT_L lw
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# define INT_S sw
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#endif
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#if (_MIPS_SZINT == 64)
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# define INT_ADD dadd
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# define INT_ADDI daddi
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# define INT_ADDU daddu
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# define INT_ADDIU daddiu
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# define INT_SUB dsub
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# define INT_SUBI dsubi
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# define INT_SUBU dsubu
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# define INT_SUBIU dsubu
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# define INT_L ld
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# define INT_S sd
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#endif
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/*
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* How to add/sub/load/store/shift C long variables.
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*/
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#if (_MIPS_SZLONG == 32)
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# define LONG_ADD add
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# define LONG_ADDI addi
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# define LONG_ADDU addu
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# define LONG_ADDIU addiu
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# define LONG_SUB sub
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# define LONG_SUBI subi
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# define LONG_SUBU subu
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# define LONG_SUBIU subu
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# define LONG_L lw
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# define LONG_S sw
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# define LONG_SLL sll
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# define LONG_SLLV sllv
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# define LONG_SRL srl
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# define LONG_SRLV srlv
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# define LONG_SRA sra
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# define LONG_SRAV srav
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#endif
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#if (_MIPS_SZLONG == 64)
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# define LONG_ADD dadd
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# define LONG_ADDI daddi
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# define LONG_ADDU daddu
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# define LONG_ADDIU daddiu
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# define LONG_SUB dsub
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# define LONG_SUBI dsubi
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# define LONG_SUBU dsubu
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# define LONG_SUBIU dsubu
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# define LONG_L ld
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# define LONG_S sd
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# define LONG_SLL dsll
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# define LONG_SLLV dsllv
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# define LONG_SRL dsrl
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# define LONG_SRLV dsrlv
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# define LONG_SRA dsra
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# define LONG_SRAV dsrav
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#endif
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/*
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* How to add/sub/load/store/shift pointers.
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*/
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#if (_MIPS_SIM == _ABIO32 && _MIPS_SZPTR == 32)
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# define PTR_ADD add
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# define PTR_ADDI addi
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# define PTR_ADDU addu
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# define PTR_ADDIU addiu
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# define PTR_SUB sub
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# define PTR_SUBI subi
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# define PTR_SUBU subu
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# define PTR_SUBIU subu
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# define PTR_L lw
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# define PTR_LA la
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# define PTR_S sw
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# define PTR_SLL sll
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# define PTR_SLLV sllv
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# define PTR_SRL srl
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# define PTR_SRLV srlv
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# define PTR_SRA sra
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# define PTR_SRAV srav
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# define PTR_SCALESHIFT 2
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#endif
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#if _MIPS_SIM == _ABIN32
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# define PTR_ADD add
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# define PTR_ADDI addi
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# define PTR_SUB sub
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# define PTR_SUBI subi
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#if __mips_isa_rev < 6
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# define PTR_ADDU add /* no u */
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# define PTR_ADDIU addi /* no u */
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# define PTR_SUBU sub /* no u */
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# define PTR_SUBIU sub /* no u */
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#else
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# define PTR_ADDU addu
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# define PTR_ADDIU addiu
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# define PTR_SUBU subu
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# define PTR_SUBIU subu
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#endif
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# define PTR_L lw
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# define PTR_LA la
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# define PTR_S sw
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# define PTR_SLL sll
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# define PTR_SLLV sllv
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# define PTR_SRL srl
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# define PTR_SRLV srlv
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# define PTR_SRA sra
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# define PTR_SRAV srav
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# define PTR_SCALESHIFT 2
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#endif
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#if (_MIPS_SIM == _ABIO32 && _MIPS_SZPTR == 64 /* o64??? */) \
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|| _MIPS_SIM == _ABI64
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# define PTR_ADD dadd
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# define PTR_ADDI daddi
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# define PTR_ADDU daddu
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# define PTR_ADDIU daddiu
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# define PTR_SUB dsub
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# define PTR_SUBI dsubi
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# define PTR_SUBU dsubu
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# define PTR_SUBIU dsubu
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# define PTR_L ld
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# define PTR_LA dla
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# define PTR_S sd
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# define PTR_SLL dsll
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# define PTR_SLLV dsllv
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# define PTR_SRL dsrl
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# define PTR_SRLV dsrlv
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# define PTR_SRA dsra
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# define PTR_SRAV dsrav
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# define PTR_SCALESHIFT 3
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#endif
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/*
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* Some cp0 registers were extended to 64bit for MIPS III.
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*/
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#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
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(_MIPS_ISA == _MIPS_ISA_MIPS32)
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# define MFC0 mfc0
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# define MTC0 mtc0
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#endif
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#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
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(_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
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# define MFC0 dmfc0
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# define MTC0 dmtc0
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#endif
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/* The MIPS architectures do not have a uniform memory model. Particular
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platforms may provide additional guarantees - for instance, the R4000
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LL and SC instructions implicitly perform a SYNC, and the 4K promises
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strong ordering.
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However, in the absence of those guarantees, we must assume weak ordering
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and SYNC explicitly where necessary.
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Some obsolete MIPS processors may not support the SYNC instruction. This
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applies to "true" MIPS I processors; most of the processors which compile
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using MIPS I implement parts of MIPS II. */
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#ifndef MIPS_SYNC
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# define MIPS_SYNC sync
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#endif
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#endif /* sys/asm.h */
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