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104 lines
2.9 KiB
ArmAsm
104 lines
2.9 KiB
ArmAsm
/* Multiple versions of strcspn
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Copyright (C) 2009, 2012 Free Software Foundation, Inc.
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Contributed by Intel Corporation.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <config.h>
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#ifdef HAVE_SSE4_SUPPORT
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#include <sysdep.h>
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#include <init-arch.h>
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#ifdef USE_AS_STRPBRK
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#define STRCSPN_SSE42 __strpbrk_sse42
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#define STRCSPN_IA32 __strpbrk_ia32
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#define __GI_STRCSPN __GI_strpbrk
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#else
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#ifndef STRCSPN
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#define STRCSPN strcspn
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#define STRCSPN_SSE42 __strcspn_sse42
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#define STRCSPN_IA32 __strcspn_ia32
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#define __GI_STRCSPN __GI_strcspn
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#endif
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#endif
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/* Define multiple versions only for the definition in libc. Don't
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define multiple versions for strpbrk in static library since we
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need strpbrk before the initialization happened. */
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#if (defined SHARED || !defined USE_AS_STRPBRK) && !defined NOT_IN_libc
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# ifdef SHARED
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.text
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ENTRY(STRCSPN)
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.type STRCSPN, @gnu_indirect_function
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pushl %ebx
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cfi_adjust_cfa_offset (4)
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cfi_rel_offset (ebx, 0)
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LOAD_PIC_REG(bx)
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cmpl $0, KIND_OFFSET+__cpu_features@GOTOFF(%ebx)
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jne 1f
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call __init_cpu_features
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1: leal STRCSPN_IA32@GOTOFF(%ebx), %eax
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testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
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jz 2f
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leal STRCSPN_SSE42@GOTOFF(%ebx), %eax
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2: popl %ebx
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cfi_adjust_cfa_offset (-4);
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cfi_restore (ebx)
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ret
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END(STRCSPN)
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# else
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.text
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ENTRY(STRCSPN)
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.type STRCSPN, @gnu_indirect_function
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cmpl $0, KIND_OFFSET+__cpu_features
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jne 1f
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call __init_cpu_features
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1: leal STRCSPN_IA32, %eax
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testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
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jz 2f
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leal STRCSPN_SSE42, %eax
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2: ret
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END(STRCSPN)
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# endif
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# undef ENTRY
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# define ENTRY(name) \
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.type STRCSPN_IA32, @function; \
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.globl STRCSPN_IA32; \
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.p2align 4; \
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STRCSPN_IA32: cfi_startproc; \
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CALL_MCOUNT
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# undef END
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# define END(name) \
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cfi_endproc; .size STRCSPN_IA32, .-STRCSPN_IA32
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# undef libc_hidden_builtin_def
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/* IFUNC doesn't work with the hidden functions in shared library since
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they will be called without setting up EBX needed for PLT which is
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used by IFUNC. */
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# define libc_hidden_builtin_def(name) \
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.globl __GI_STRCSPN; __GI_STRCSPN = STRCSPN_IA32
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#endif
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#endif /* HAVE_SSE4_SUPPORT */
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#ifdef USE_AS_STRPBRK
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#include "../../strpbrk.S"
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#else
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#include "../../strcspn.S"
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#endif
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