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This patch optimizes the generic spinlock code. The type pthread_spinlock_t is a typedef to volatile int on all archs. Passing a volatile pointer to the atomic macros which are not mapped to the C11 atomic builtins can lead to extra stores and loads to stack if such a macro creates a temporary variable by using "__typeof (*(mem)) tmp;". Thus, those macros which are used by spinlock code - atomic_exchange_acquire, atomic_load_relaxed, atomic_compare_exchange_weak - have to be adjusted. According to the comment from Szabolcs Nagy, the type of a cast expression is unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm): __typeof ((__typeof (*(mem)) *(mem)) tmp; Thus from spinlock perspective the variable tmp is of type int instead of type volatile int. This patch adjusts those macros in include/atomic.h. With this construct GCC >= 5 omits the extra stores and loads. The atomic macros are replaced by the C11 like atomic macros and thus the code is aligned to it. The pthread_spin_unlock implementation is now using release memory order instead of sequentially consistent memory order. The issue with passed volatile int pointers applies to the C11 like atomic macros as well as the ones used before. I've added a glibc_likely hint to the first atomic exchange in pthread_spin_lock in order to return immediately to the caller if the lock is free. Without the hint, there is an additional jump if the lock is free. I've added the atomic_spin_nop macro within the loop of plain reads. The plain reads are also realized by C11 like atomic_load_relaxed macro. The new define ATOMIC_EXCHANGE_USES_CAS determines if the first try to acquire the spinlock in pthread_spin_lock or pthread_spin_trylock is an exchange or a CAS. This is defined in atomic-machine.h for all architectures. The define SPIN_LOCK_READS_BETWEEN_CMPXCHG is now removed. There is no technical reason for throwing in a CAS every now and then, and so far we have no evidence that it can improve performance. If that would be the case, we have to adjust other spin-waiting loops elsewhere, too! Using a CAS loop without plain reads is not a good idea on many targets and wasn't used by one. Thus there is now no option to do so. Architectures are now using the generic spinlock automatically if they do not provide an own implementation. Thus the pthread_spin_lock.c files in sysdeps folder are deleted. ChangeLog: * NEWS: Mention new spinlock implementation. * include/atomic.h: (__atomic_val_bysize): Cast type to omit volatile qualifier. (atomic_exchange_acq): Likewise. (atomic_load_relaxed): Likewise. (ATOMIC_EXCHANGE_USES_CAS): Check definition. * nptl/pthread_spin_init.c (pthread_spin_init): Use atomic_store_relaxed. * nptl/pthread_spin_lock.c (pthread_spin_lock): Use C11-like atomic macros. * nptl/pthread_spin_trylock.c (pthread_spin_trylock): Likewise. * nptl/pthread_spin_unlock.c (pthread_spin_unlock): Use atomic_store_release. * sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File. * sysdeps/arm/nptl/pthread_spin_lock.c: Likewise. * sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise. * sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise. * sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise. * sysdeps/mips/nptl/pthread_spin_lock.c: Likewise. * sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise. * sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS): Define. * sysdeps/alpha/atomic-machine.h: Likewise. * sysdeps/arm/atomic-machine.h: Likewise. * sysdeps/i386/atomic-machine.h: Likewise. * sysdeps/ia64/atomic-machine.h: Likewise. * sysdeps/m68k/coldfire/atomic-machine.h: Likewise. * sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise. * sysdeps/microblaze/atomic-machine.h: Likewise. * sysdeps/mips/atomic-machine.h: Likewise. * sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise. * sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise. * sysdeps/s390/atomic-machine.h: Likewise. * sysdeps/sparc/sparc32/atomic-machine.h: Likewise. * sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise. * sysdeps/sparc/sparc64/atomic-machine.h: Likewise. * sysdeps/tile/tilegx/atomic-machine.h: Likewise. * sysdeps/tile/tilepro/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise. * sysdeps/x86_64/atomic-machine.h: Likewise.
243 lines
8.6 KiB
C
243 lines
8.6 KiB
C
/* Atomic operations. PowerPC64 version.
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Copyright (C) 2003-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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/* POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
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This is a hint to the hardware to expect additional updates adjacent
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to the lock word or not. If we are acquiring a Mutex, the hint
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should be true. Otherwise we releasing a Mutex or doing a simple
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atomic operation. In that case we don't expect additional updates
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adjacent to the lock word after the Store Conditional and the hint
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should be false. */
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#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
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# define MUTEX_HINT_ACQ ",1"
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# define MUTEX_HINT_REL ",0"
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#else
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# define MUTEX_HINT_ACQ
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# define MUTEX_HINT_REL
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#endif
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#define __HAVE_64B_ATOMICS 1
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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#define ATOMIC_EXCHANGE_USES_CAS 1
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/* The 32-bit exchange_bool is different on powerpc64 because the subf
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does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
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(a load word and zero (high 32) form) load.
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In powerpc64 register values are 64-bit by default, including oldval.
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The value in old val unknown sign extension, lwarx loads the 32-bit
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value as unsigned. So we explicitly clear the high 32 bits in oldval. */
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#define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
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({ \
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unsigned int __tmp, __tmp2; \
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__asm __volatile (" clrldi %1,%1,32\n" \
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"1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
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" subf. %0,%1,%0\n" \
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" bne 2f\n" \
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" stwcx. %4,0,%2\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp), "=r" (__tmp2) \
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: "b" (mem), "1" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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/*
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* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
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* and Store doubleword conditional indexed (stdcx) instructions. So here
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* we define the 64-bit forms.
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*/
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#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
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({ \
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unsigned long __tmp; \
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__asm __volatile ( \
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"1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
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" subf. %0,%2,%0\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (mem), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp != 0; \
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})
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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__asm __volatile ( \
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"1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
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" cmpd %0,%2\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&r" (__tmp) \
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: "b" (__memp), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp; \
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})
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#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \
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" cmpd %0,%2\n" \
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" bne 2f\n" \
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" stdcx. %3,0,%1\n" \
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" bne- 1b\n" \
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"2: " \
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: "=&r" (__tmp) \
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: "b" (__memp), "r" (oldval), "r" (newval) \
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: "cr0", "memory"); \
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__tmp; \
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})
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#define __arch_atomic_exchange_64_acq(mem, value) \
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({ \
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__typeof (*mem) __val; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
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" stdcx. %3,0,%2\n" \
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" bne- 1b\n" \
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" " __ARCH_ACQ_INSTR \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_64_rel(mem, value) \
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({ \
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__typeof (*mem) __val; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%2" MUTEX_HINT_REL "\n" \
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" stdcx. %3,0,%2\n" \
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" bne- 1b" \
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: "=&r" (__val), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_and_add_64(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_and_add_64_acq(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3" MUTEX_HINT_ACQ "\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b\n" \
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__ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_exchange_and_add_64_rel(mem, value) \
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({ \
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__typeof (*mem) __val, __tmp; \
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__asm __volatile (__ARCH_REL_INSTR "\n" \
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"1: ldarx %0,0,%3" MUTEX_HINT_REL "\n" \
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" add %1,%0,%4\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b" \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "r" (value), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_increment_val_64(mem) \
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({ \
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__typeof (*(mem)) __val; \
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__asm __volatile ("1: ldarx %0,0,%2\n" \
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" addi %0,%0,1\n" \
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" stdcx. %0,0,%2\n" \
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" bne- 1b" \
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: "=&b" (__val), "=m" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_decrement_val_64(mem) \
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({ \
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__typeof (*(mem)) __val; \
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__asm __volatile ("1: ldarx %0,0,%2\n" \
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" subi %0,%0,1\n" \
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" stdcx. %0,0,%2\n" \
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" bne- 1b" \
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: "=&b" (__val), "=m" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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#define __arch_atomic_decrement_if_positive_64(mem) \
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({ int __val, __tmp; \
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__asm __volatile ("1: ldarx %0,0,%3\n" \
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" cmpdi 0,%0,0\n" \
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" addi %1,%0,-1\n" \
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" ble 2f\n" \
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" stdcx. %1,0,%3\n" \
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" bne- 1b\n" \
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"2: " __ARCH_ACQ_INSTR \
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: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
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: "b" (mem), "m" (*mem) \
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: "cr0", "memory"); \
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__val; \
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})
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/*
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* All powerpc64 processors support the new "light weight" sync (lwsync).
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*/
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#define atomic_read_barrier() __asm ("lwsync" ::: "memory")
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/*
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* "light weight" sync can also be used for the release barrier.
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*/
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#ifndef UP
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# define __ARCH_REL_INSTR "lwsync"
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#endif
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#define atomic_write_barrier() __asm ("lwsync" ::: "memory")
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/*
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* Include the rest of the atomic ops macros which are common to both
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* powerpc32 and powerpc64.
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*/
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#include_next <atomic-machine.h>
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