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e162ab2bf1
ThunderX1 and ThunderX2 have been retired for a few years now.
So let's remove the thunderx{,2} specific versions of memcpy.
The performance gain or them was for medium and large sizes
while the generic (aarch64) memcpy will handle just slightly worse.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
70 lines
2.5 KiB
C
70 lines
2.5 KiB
C
/* Initialize CPU feature data. AArch64 version.
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This file is part of the GNU C Library.
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Copyright (C) 2017-2024 Free Software Foundation, Inc.
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Copyright The GNU Toolchain Authors.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _CPU_FEATURES_AARCH64_H
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#define _CPU_FEATURES_AARCH64_H
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#include <stdint.h>
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#include <stdbool.h>
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#define MIDR_PARTNUM_SHIFT 4
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#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
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#define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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#define MIDR_ARCHITECTURE_SHIFT 16
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#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_VARIANT_SHIFT 20
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#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
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#define MIDR_VARIANT(midr) \
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(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
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#define MIDR_IMPLEMENTOR_SHIFT 24
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#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_IMPLEMENTOR(midr) \
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define IS_EMAG(midr) (MIDR_IMPLEMENTOR(midr) == 'P' \
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&& MIDR_PARTNUM(midr) == 0x000)
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#define IS_KUNPENG920(midr) (MIDR_IMPLEMENTOR(midr) == 'H' \
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&& MIDR_PARTNUM(midr) == 0xd01)
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#define IS_A64FX(midr) (MIDR_IMPLEMENTOR(midr) == 'F' \
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&& MIDR_PARTNUM(midr) == 0x001)
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#define IS_ORYON1(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \
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&& (MIDR_PARTNUM(midr) == 0x001 \
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|| (MIDR_PARTNUM(midr) == 0x002 \
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&& MIDR_VARIANT(midr) == 0)))
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struct cpu_features
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{
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uint64_t midr_el1;
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unsigned zva_size;
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bool bti;
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/* Currently, the GLIBC memory tagging tunable only defines 8 bits. */
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uint8_t mte_state;
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bool sve;
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bool prefer_sve_ifuncs;
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bool mops;
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};
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#endif /* _CPU_FEATURES_AARCH64_H */
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