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581c785bf3
I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 7061 files FOO. I then removed trailing white space from math/tgmath.h, support/tst-support-open-dev-null-range.c, and sysdeps/x86_64/multiarch/strlen-vec.S, to work around the following obscure pre-commit check failure diagnostics from Savannah. I don't know why I run into these diagnostics whereas others evidently do not. remote: *** 912-#endif remote: *** 913: remote: *** 914- remote: *** error: lines with trailing whitespace found ... remote: *** error: sysdeps/unix/sysv/linux/statx_cp.c: trailing lines
63 lines
1.5 KiB
ArmAsm
63 lines
1.5 KiB
ArmAsm
;! HP-PA __mpn_rshift --
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;! Copyright (C) 1992-2022 Free Software Foundation, Inc.
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;! This file is part of the GNU MP Library.
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;! The GNU MP Library is free software; you can redistribute it and/or modify
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;! it under the terms of the GNU Lesser General Public License as published by
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;! the Free Software Foundation; either version 2.1 of the License, or (at your
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;! option) any later version.
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;! The GNU MP Library is distributed in the hope that it will be useful, but
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;! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;! or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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;! License for more details.
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;! You should have received a copy of the GNU Lesser General Public License
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;! along with the GNU MP Library. If not, see
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;! <https://www.gnu.org/licenses/>.
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;! INPUT PARAMETERS
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;! res_ptr gr26
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;! s_ptr gr25
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;! size gr24
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;! cnt gr23
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.text
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.export __mpn_rshift
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__mpn_rshift:
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.proc
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.callinfo frame=64,no_calls
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.entry
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ldws,ma 4(%r25),%r22
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mtsar %r23
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addib,= -1,%r24,L$0004
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vshd %r22,%r0,%r28 ;! compute carry out limb
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ldws,ma 4(%r25),%r29
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addib,= -1,%r24,L$0002
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vshd %r29,%r22,%r20
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L$loop: ldws,ma 4(%r25),%r22
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stws,ma %r20,4(%r26)
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addib,= -1,%r24,L$0003
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vshd %r22,%r29,%r20
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ldws,ma 4(%r25),%r29
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stws,ma %r20,4(%r26)
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addib,<> -1,%r24,L$loop
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vshd %r29,%r22,%r20
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L$0002: stws,ma %r20,4(%r26)
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vshd %r0,%r29,%r20
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bv 0(%r2)
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stw %r20,0(%r26)
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L$0003: stws,ma %r20,4(%r26)
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L$0004: vshd %r0,%r22,%r20
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bv 0(%r2)
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stw %r20,0(%r26)
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.exit
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.procend
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