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I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
348 lines
8.2 KiB
ArmAsm
348 lines
8.2 KiB
ArmAsm
/* Copy SIZE bytes from SRC to DEST. For SUN4V Niagara.
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Copyright (C) 2006-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by David S. Miller (davem@davemloft.net)
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#define ASI_BLK_INIT_QUAD_LDD_P 0xe2
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#define ASI_P 0x80
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#define ASI_PNF 0x82
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#define LOAD(type,addr,dest) type##a [addr] ASI_P, dest
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#define LOAD_TWIN(addr_reg,dest0,dest1) \
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ldda [addr_reg] ASI_BLK_INIT_QUAD_LDD_P, dest0
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#define STORE(type,src,addr) type src, [addr]
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#define STORE_INIT(src,addr) stxa src, [addr] %asi
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#ifndef XCC
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#define USE_BPR
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#define XCC xcc
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#endif
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#if IS_IN (libc)
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.register %g2,#scratch
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.register %g3,#scratch
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.register %g6,#scratch
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.text
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ENTRY(__mempcpy_niagara1)
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ba,pt %XCC, 101f
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add %o0, %o2, %g5
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END(__mempcpy_niagara1)
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.align 32
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ENTRY(__memcpy_niagara1)
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100: /* %o0=dst, %o1=src, %o2=len */
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mov %o0, %g5
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101:
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# ifndef USE_BPR
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srl %o2, 0, %o2
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# endif
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cmp %o2, 0
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be,pn %XCC, 85f
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218: or %o0, %o1, %o3
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cmp %o2, 16
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blu,a,pn %XCC, 80f
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or %o3, %o2, %o3
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/* 2 blocks (128 bytes) is the minimum we can do the block
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* copy with. We need to ensure that we'll iterate at least
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* once in the block copy loop. At worst we'll need to align
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* the destination to a 64-byte boundary which can chew up
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* to (64 - 1) bytes from the length before we perform the
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* block copy loop.
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*/
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cmp %o2, (2 * 64)
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blu,pt %XCC, 70f
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andcc %o3, 0x7, %g0
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/* %o0: dst
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* %o1: src
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* %o2: len (known to be >= 128)
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*
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* The block copy loops will use %o4/%o5,%g2/%g3 as
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* temporaries while copying the data.
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*/
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LOAD(prefetch, %o1, #one_read)
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wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
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/* Align destination on 64-byte boundary. */
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andcc %o0, (64 - 1), %o4
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be,pt %XCC, 2f
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sub %o4, 64, %o4
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sub %g0, %o4, %o4 ! bytes to align dst
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sub %o2, %o4, %o2
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1: subcc %o4, 1, %o4
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LOAD(ldub, %o1, %g1)
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STORE(stb, %g1, %o0)
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add %o1, 1, %o1
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bne,pt %XCC, 1b
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add %o0, 1, %o0
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/* If the source is on a 16-byte boundary we can do
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* the direct block copy loop. If it is 8-byte aligned
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* we can do the 16-byte loads offset by -8 bytes and the
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* init stores offset by one register.
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*
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* If the source is not even 8-byte aligned, we need to do
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* shifting and masking (basically integer faligndata).
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*
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* The careful bit with init stores is that if we store
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* to any part of the cache line we have to store the whole
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* cacheline else we can end up with corrupt L2 cache line
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* contents. Since the loop works on 64-bytes of 64-byte
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* aligned store data at a time, this is easy to ensure.
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*/
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2:
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andcc %o1, (16 - 1), %o4
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andn %o2, (64 - 1), %g1 ! block copy loop iterator
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sub %o2, %g1, %o2 ! final sub-block copy bytes
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be,pt %XCC, 50f
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cmp %o4, 8
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be,a,pt %XCC, 10f
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sub %o1, 0x8, %o1
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/* Neither 8-byte nor 16-byte aligned, shift and mask. */
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mov %g1, %o4
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and %o1, 0x7, %g1
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sll %g1, 3, %g1
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mov 64, %o3
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andn %o1, 0x7, %o1
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LOAD(ldx, %o1, %g2)
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sub %o3, %g1, %o3
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sllx %g2, %g1, %g2
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#define SWIVEL_ONE_DWORD(SRC, TMP1, TMP2, PRE_VAL, PRE_SHIFT, POST_SHIFT, DST)\
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LOAD(ldx, SRC, TMP1); \
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srlx TMP1, PRE_SHIFT, TMP2; \
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or TMP2, PRE_VAL, TMP2; \
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STORE_INIT(TMP2, DST); \
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sllx TMP1, POST_SHIFT, PRE_VAL;
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1: add %o1, 0x8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x00)
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add %o1, 0x8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x08)
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add %o1, 0x8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x10)
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add %o1, 0x8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x18)
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add %o1, 32, %o1
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LOAD(prefetch, %o1, #one_read)
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sub %o1, 32 - 8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x20)
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add %o1, 8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x28)
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add %o1, 8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x30)
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add %o1, 8, %o1
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SWIVEL_ONE_DWORD(%o1, %g3, %o5, %g2, %o3, %g1, %o0 + 0x38)
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subcc %o4, 64, %o4
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bne,pt %XCC, 1b
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add %o0, 64, %o0
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#undef SWIVEL_ONE_DWORD
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srl %g1, 3, %g1
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ba,pt %XCC, 60f
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add %o1, %g1, %o1
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10: /* Destination is 64-byte aligned, source was only 8-byte
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* aligned but it has been subtracted by 8 and we perform
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* one twin load ahead, then add 8 back into source when
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* we finish the loop.
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*/
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LOAD_TWIN(%o1, %o4, %o5)
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1: add %o1, 16, %o1
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LOAD_TWIN(%o1, %g2, %g3)
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add %o1, 16 + 32, %o1
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LOAD(prefetch, %o1, #one_read)
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sub %o1, 32, %o1
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STORE_INIT(%o5, %o0 + 0x00) ! initializes cache line
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STORE_INIT(%g2, %o0 + 0x08)
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LOAD_TWIN(%o1, %o4, %o5)
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add %o1, 16, %o1
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STORE_INIT(%g3, %o0 + 0x10)
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STORE_INIT(%o4, %o0 + 0x18)
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LOAD_TWIN(%o1, %g2, %g3)
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add %o1, 16, %o1
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STORE_INIT(%o5, %o0 + 0x20)
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STORE_INIT(%g2, %o0 + 0x28)
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LOAD_TWIN(%o1, %o4, %o5)
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STORE_INIT(%g3, %o0 + 0x30)
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STORE_INIT(%o4, %o0 + 0x38)
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subcc %g1, 64, %g1
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bne,pt %XCC, 1b
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add %o0, 64, %o0
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ba,pt %XCC, 60f
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add %o1, 0x8, %o1
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50: /* Destination is 64-byte aligned, and source is 16-byte
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* aligned.
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*/
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1: LOAD_TWIN(%o1, %o4, %o5)
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add %o1, 16, %o1
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LOAD_TWIN(%o1, %g2, %g3)
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add %o1, 16 + 32, %o1
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LOAD(prefetch, %o1, #one_read)
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sub %o1, 32, %o1
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STORE_INIT(%o4, %o0 + 0x00) ! initializes cache line
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STORE_INIT(%o5, %o0 + 0x08)
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LOAD_TWIN(%o1, %o4, %o5)
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add %o1, 16, %o1
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STORE_INIT(%g2, %o0 + 0x10)
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STORE_INIT(%g3, %o0 + 0x18)
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LOAD_TWIN(%o1, %g2, %g3)
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add %o1, 16, %o1
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STORE_INIT(%o4, %o0 + 0x20)
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STORE_INIT(%o5, %o0 + 0x28)
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STORE_INIT(%g2, %o0 + 0x30)
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STORE_INIT(%g3, %o0 + 0x38)
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subcc %g1, 64, %g1
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bne,pt %XCC, 1b
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add %o0, 64, %o0
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/* fall through */
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60:
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/* %o2 contains any final bytes still needed to be copied
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* over. If anything is left, we copy it one byte at a time.
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*/
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wr %g0, ASI_PNF, %asi
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brz,pt %o2, 85f
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sub %o0, %o1, %o3
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ba,a,pt %XCC, 90f
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.align 64
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70: /* 16 < len <= 64 */
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bne,pn %XCC, 75f
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sub %o0, %o1, %o3
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72:
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andn %o2, 0xf, %o4
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and %o2, 0xf, %o2
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1: subcc %o4, 0x10, %o4
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LOAD(ldx, %o1, %o5)
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add %o1, 0x08, %o1
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LOAD(ldx, %o1, %g1)
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sub %o1, 0x08, %o1
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STORE(stx, %o5, %o1 + %o3)
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add %o1, 0x8, %o1
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STORE(stx, %g1, %o1 + %o3)
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bgu,pt %XCC, 1b
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add %o1, 0x8, %o1
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73: andcc %o2, 0x8, %g0
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be,pt %XCC, 1f
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nop
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sub %o2, 0x8, %o2
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LOAD(ldx, %o1, %o5)
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STORE(stx, %o5, %o1 + %o3)
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add %o1, 0x8, %o1
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1: andcc %o2, 0x4, %g0
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be,pt %XCC, 1f
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nop
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sub %o2, 0x4, %o2
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LOAD(lduw, %o1, %o5)
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STORE(stw, %o5, %o1 + %o3)
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add %o1, 0x4, %o1
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1: cmp %o2, 0
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be,pt %XCC, 85f
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nop
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ba,pt %XCC, 90f
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nop
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75:
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andcc %o0, 0x7, %g1
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sub %g1, 0x8, %g1
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be,pn %icc, 2f
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sub %g0, %g1, %g1
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sub %o2, %g1, %o2
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1: subcc %g1, 1, %g1
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LOAD(ldub, %o1, %o5)
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STORE(stb, %o5, %o1 + %o3)
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bgu,pt %icc, 1b
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add %o1, 1, %o1
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2: add %o1, %o3, %o0
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andcc %o1, 0x7, %g1
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bne,pt %icc, 8f
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sll %g1, 3, %g1
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cmp %o2, 16
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bgeu,pt %icc, 72b
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nop
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ba,a,pt %XCC, 73b
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8: mov 64, %o3
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andn %o1, 0x7, %o1
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LOAD(ldx, %o1, %g2)
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sub %o3, %g1, %o3
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andn %o2, 0x7, %o4
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sllx %g2, %g1, %g2
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1: add %o1, 0x8, %o1
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LOAD(ldx, %o1, %g3)
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subcc %o4, 0x8, %o4
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srlx %g3, %o3, %o5
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or %o5, %g2, %o5
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STORE(stx, %o5, %o0)
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add %o0, 0x8, %o0
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bgu,pt %icc, 1b
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sllx %g3, %g1, %g2
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srl %g1, 3, %g1
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andcc %o2, 0x7, %o2
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be,pn %icc, 85f
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add %o1, %g1, %o1
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ba,pt %XCC, 90f
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sub %o0, %o1, %o3
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.align 64
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80: /* 0 < len <= 16 */
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andcc %o3, 0x3, %g0
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bne,pn %XCC, 90f
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sub %o0, %o1, %o3
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1:
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subcc %o2, 4, %o2
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LOAD(lduw, %o1, %g1)
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STORE(stw, %g1, %o1 + %o3)
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bgu,pt %XCC, 1b
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add %o1, 4, %o1
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85: retl
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mov %g5, %o0
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.align 32
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90:
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subcc %o2, 1, %o2
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LOAD(ldub, %o1, %g1)
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STORE(stb, %g1, %o1 + %o3)
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bgu,pt %XCC, 90b
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add %o1, 1, %o1
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retl
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mov %g5, %o0
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END(__memcpy_niagara1)
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#endif
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