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ceabdcd130
1. Add default ISA level selection in non-multiarch/rtld
implementations.
2. Add ISA level build guards to different implementations.
- I.e strcmp-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to
include it as we will always use one of the ISA level 4
implementations (strcmp-evex.S).
3. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
360 lines
7.6 KiB
ArmAsm
360 lines
7.6 KiB
ArmAsm
/* memrchr optimized with SSE2.
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Copyright (C) 2017-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation
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so we need this to build for ISA V2 builds. */
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#if ISA_SHOULD_BUILD (2)
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# ifndef MEMRCHR
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# define MEMRCHR __memrchr_sse2
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# endif
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# include <sysdep.h>
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# define VEC_SIZE 16
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# define PAGE_SIZE 4096
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.text
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ENTRY_P2ALIGN(MEMRCHR, 6)
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# ifdef __ILP32__
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/* Clear upper bits. */
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mov %RDX_LP, %RDX_LP
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# endif
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movd %esi, %xmm0
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/* Get end pointer. */
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leaq (%rdx, %rdi), %rcx
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punpcklbw %xmm0, %xmm0
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punpcklwd %xmm0, %xmm0
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pshufd $0, %xmm0, %xmm0
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/* Check if we can load 1x VEC without cross a page. */
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testl $(PAGE_SIZE - VEC_SIZE), %ecx
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jz L(page_cross)
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/* NB: This load happens regardless of whether rdx (len) is zero. Since
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it doesn't cross a page and the standard gurantees any pointer have
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at least one-valid byte this load must be safe. For the entire
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history of the x86 memrchr implementation this has been possible so
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no code "should" be relying on a zero-length check before this load.
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The zero-length check is moved to the page cross case because it is
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1) pretty cold and including it pushes the hot case len <= VEC_SIZE
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into 2-cache lines. */
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movups -(VEC_SIZE)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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subq $VEC_SIZE, %rdx
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ja L(more_1x_vec)
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L(ret_vec_x0_test):
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/* Zero-flag set if eax (src) is zero. Destination unchanged if src is
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zero. */
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bsrl %eax, %eax
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jz L(ret_0)
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/* Check if the CHAR match is in bounds. Need to truly zero `eax` here
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if out of bounds. */
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addl %edx, %eax
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jl L(zero_0)
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/* Since we subtracted VEC_SIZE from rdx earlier we can just add to base
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ptr. */
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addq %rdi, %rax
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L(ret_0):
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ret
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.p2align 4,, 5
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L(ret_vec_x0):
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bsrl %eax, %eax
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leaq -(VEC_SIZE)(%rcx, %rax), %rax
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ret
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.p2align 4,, 2
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L(zero_0):
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xorl %eax, %eax
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ret
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.p2align 4,, 8
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L(more_1x_vec):
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testl %eax, %eax
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jnz L(ret_vec_x0)
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/* Align rcx (pointer to string). */
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decq %rcx
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andq $-VEC_SIZE, %rcx
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movq %rcx, %rdx
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/* NB: We could consistenyl save 1-byte in this pattern with `movaps
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%xmm0, %xmm1; pcmpeq IMM8(r), %xmm1; ...`. The reason against it is
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it adds more frontend uops (even if the moves can be eliminated) and
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some percentage of the time actual backend uops. */
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movaps -(VEC_SIZE)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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subq %rdi, %rdx
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pmovmskb %xmm1, %eax
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cmpq $(VEC_SIZE * 2), %rdx
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ja L(more_2x_vec)
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L(last_2x_vec):
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subl $VEC_SIZE, %edx
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jbe L(ret_vec_x0_test)
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testl %eax, %eax
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jnz L(ret_vec_x0)
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movaps -(VEC_SIZE * 2)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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subl $VEC_SIZE, %edx
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bsrl %eax, %eax
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jz L(ret_1)
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addl %edx, %eax
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jl L(zero_0)
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addq %rdi, %rax
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L(ret_1):
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ret
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/* Don't align. Otherwise lose 2-byte encoding in jump to L(page_cross)
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causes the hot pause (length <= VEC_SIZE) to span multiple cache
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lines. Naturally aligned % 16 to 8-bytes. */
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L(page_cross):
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/* Zero length check. */
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testq %rdx, %rdx
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jz L(zero_0)
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leaq -1(%rcx), %r8
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andq $-(VEC_SIZE), %r8
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movaps (%r8), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %esi
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/* Shift out negative alignment (because we are starting from endptr and
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working backwards). */
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negl %ecx
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/* 32-bit shift but VEC_SIZE=16 so need to mask the shift count
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explicitly. */
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andl $(VEC_SIZE - 1), %ecx
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shl %cl, %esi
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movzwl %si, %eax
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leaq (%rdi, %rdx), %rcx
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cmpq %rdi, %r8
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ja L(more_1x_vec)
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subl $VEC_SIZE, %edx
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bsrl %eax, %eax
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jz L(ret_2)
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addl %edx, %eax
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jl L(zero_1)
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addq %rdi, %rax
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L(ret_2):
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ret
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/* Fits in aliging bytes. */
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L(zero_1):
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xorl %eax, %eax
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ret
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.p2align 4,, 5
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L(ret_vec_x1):
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bsrl %eax, %eax
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leaq -(VEC_SIZE * 2)(%rcx, %rax), %rax
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ret
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.p2align 4,, 8
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L(more_2x_vec):
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testl %eax, %eax
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jnz L(ret_vec_x0)
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movaps -(VEC_SIZE * 2)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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testl %eax, %eax
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jnz L(ret_vec_x1)
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movaps -(VEC_SIZE * 3)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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subq $(VEC_SIZE * 4), %rdx
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ja L(more_4x_vec)
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addl $(VEC_SIZE), %edx
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jle L(ret_vec_x2_test)
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L(last_vec):
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testl %eax, %eax
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jnz L(ret_vec_x2)
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movaps -(VEC_SIZE * 4)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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subl $(VEC_SIZE), %edx
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bsrl %eax, %eax
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jz L(ret_3)
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addl %edx, %eax
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jl L(zero_2)
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addq %rdi, %rax
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L(ret_3):
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ret
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.p2align 4,, 6
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L(ret_vec_x2_test):
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bsrl %eax, %eax
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jz L(zero_2)
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addl %edx, %eax
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jl L(zero_2)
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addq %rdi, %rax
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ret
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L(zero_2):
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xorl %eax, %eax
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ret
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.p2align 4,, 5
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L(ret_vec_x2):
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bsrl %eax, %eax
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leaq -(VEC_SIZE * 3)(%rcx, %rax), %rax
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ret
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.p2align 4,, 5
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L(ret_vec_x3):
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bsrl %eax, %eax
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leaq -(VEC_SIZE * 4)(%rcx, %rax), %rax
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ret
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.p2align 4,, 8
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L(more_4x_vec):
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testl %eax, %eax
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jnz L(ret_vec_x2)
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movaps -(VEC_SIZE * 4)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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testl %eax, %eax
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jnz L(ret_vec_x3)
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addq $-(VEC_SIZE * 4), %rcx
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_4x_vec)
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/* Offset everything by 4x VEC_SIZE here to save a few bytes at the end
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keeping the code from spilling to the next cache line. */
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addq $(VEC_SIZE * 4 - 1), %rcx
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andq $-(VEC_SIZE * 4), %rcx
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leaq (VEC_SIZE * 4)(%rdi), %rdx
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andq $-(VEC_SIZE * 4), %rdx
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.p2align 4,, 11
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L(loop_4x_vec):
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movaps (VEC_SIZE * -1)(%rcx), %xmm1
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movaps (VEC_SIZE * -2)(%rcx), %xmm2
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movaps (VEC_SIZE * -3)(%rcx), %xmm3
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movaps (VEC_SIZE * -4)(%rcx), %xmm4
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pcmpeqb %xmm0, %xmm1
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pcmpeqb %xmm0, %xmm2
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pcmpeqb %xmm0, %xmm3
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pcmpeqb %xmm0, %xmm4
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por %xmm1, %xmm2
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por %xmm3, %xmm4
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por %xmm2, %xmm4
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pmovmskb %xmm4, %esi
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testl %esi, %esi
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jnz L(loop_end)
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addq $-(VEC_SIZE * 4), %rcx
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cmpq %rdx, %rcx
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jne L(loop_4x_vec)
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subl %edi, %edx
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/* Ends up being 1-byte nop. */
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.p2align 4,, 2
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L(last_4x_vec):
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movaps -(VEC_SIZE)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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cmpl $(VEC_SIZE * 2), %edx
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jbe L(last_2x_vec)
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testl %eax, %eax
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jnz L(ret_vec_x0)
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movaps -(VEC_SIZE * 2)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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testl %eax, %eax
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jnz L(ret_vec_end)
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movaps -(VEC_SIZE * 3)(%rcx), %xmm1
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pcmpeqb %xmm0, %xmm1
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pmovmskb %xmm1, %eax
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subl $(VEC_SIZE * 3), %edx
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ja L(last_vec)
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bsrl %eax, %eax
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jz L(ret_4)
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addl %edx, %eax
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jl L(zero_3)
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addq %rdi, %rax
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L(ret_4):
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ret
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/* Ends up being 1-byte nop. */
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.p2align 4,, 3
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L(loop_end):
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pmovmskb %xmm1, %eax
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sall $16, %eax
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jnz L(ret_vec_end)
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pmovmskb %xmm2, %eax
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testl %eax, %eax
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jnz L(ret_vec_end)
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pmovmskb %xmm3, %eax
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/* Combine last 2 VEC matches. If ecx (VEC3) is zero (no CHAR in VEC3)
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then it won't affect the result in esi (VEC4). If ecx is non-zero
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then CHAR in VEC3 and bsrq will use that position. */
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sall $16, %eax
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orl %esi, %eax
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bsrl %eax, %eax
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leaq -(VEC_SIZE * 4)(%rcx, %rax), %rax
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ret
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L(ret_vec_end):
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bsrl %eax, %eax
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leaq (VEC_SIZE * -2)(%rax, %rcx), %rax
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ret
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/* Use in L(last_4x_vec). In the same cache line. This is just a spare
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aligning bytes. */
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L(zero_3):
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xorl %eax, %eax
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ret
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/* 2-bytes from next cache line. */
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END(MEMRCHR)
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#endif
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