mirror of
https://sourceware.org/git/glibc.git
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69717709ec
Size Optimizations:
1. Condence hot path for better cache-locality.
- This is most impact for strchrnul where the logic strings with
len <= VEC_SIZE or with a match in the first VEC no fits entirely
in the first cache line.
2. Reuse common targets in first 4x VEC and after the loop.
3. Don't align targets so aggressively if it doesn't change the number
of fetch blocks it will require and put more care in avoiding the
case where targets unnecessarily split cache lines.
4. Align the loop better for DSB/LSD
5. Use more code-size efficient instructions.
- tzcnt ... -> bsf ...
- vpcmpb $0 ... -> vpcmpeq ...
6. Align labels less aggressively, especially if it doesn't save fetch
blocks / causes the basic-block to span extra cache-lines.
Code Size Changes:
strchr-evex.S : -63 bytes
strchrnul-evex.S: -48 bytes
Net perf changes:
Reported as geometric mean of all improvements / regressions from N=10
runs of the benchtests. Value as New Time / Old Time so < 1.0 is
improvement and 1.0 is regression.
strchr-evex.S (Fixed) : 0.971
strchr-evex.S (Rand) : 0.932
strchrnul-evex.S : 0.965
Full results attached in email.
Full check passes on x86-64.
518 lines
14 KiB
ArmAsm
518 lines
14 KiB
ArmAsm
/* strchr/strchrnul optimized with 256-bit EVEX instructions.
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Copyright (C) 2021-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (4)
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# include <sysdep.h>
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# ifndef STRCHR
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# define STRCHR __strchr_evex
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# endif
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# ifndef VEC_SIZE
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# include "x86-evex256-vecs.h"
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# endif
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# ifdef USE_AS_WCSCHR
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# define VPBROADCAST vpbroadcastd
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# define VPCMP vpcmpd
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# define VPCMPEQ vpcmpeqd
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# define VPTESTN vptestnmd
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# define VPTEST vptestmd
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# define VPMINU vpminud
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# define CHAR_REG esi
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# define SHIFT_REG rcx
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# define CHAR_SIZE 4
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# define USE_WIDE_CHAR
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# else
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# define VPBROADCAST vpbroadcastb
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# define VPCMP vpcmpb
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# define VPCMPEQ vpcmpeqb
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# define VPTESTN vptestnmb
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# define VPTEST vptestmb
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# define VPMINU vpminub
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# define CHAR_REG sil
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# define SHIFT_REG rdi
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# define CHAR_SIZE 1
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# endif
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# include "reg-macros.h"
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# if VEC_SIZE == 64
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# define MASK_GPR rcx
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# define LOOP_REG rax
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# define COND_MASK(k_reg) {%k_reg}
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# else
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# define MASK_GPR rax
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# define LOOP_REG rdi
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# define COND_MASK(k_reg)
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# endif
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# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE)
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# if CHAR_PER_VEC == 64
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# define LAST_VEC_OFFSET (VEC_SIZE * 3)
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# define TESTZ(reg) incq %VGPR_SZ(reg, 64)
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# else
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# if CHAR_PER_VEC == 32
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# define TESTZ(reg) incl %VGPR_SZ(reg, 32)
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# elif CHAR_PER_VEC == 16
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# define TESTZ(reg) incw %VGPR_SZ(reg, 16)
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# else
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# define TESTZ(reg) incb %VGPR_SZ(reg, 8)
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# endif
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# define LAST_VEC_OFFSET (VEC_SIZE * 2)
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# endif
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# define VMATCH VMM(0)
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# define PAGE_SIZE 4096
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.section SECTION(.text), "ax", @progbits
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ENTRY_P2ALIGN (STRCHR, 6)
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/* Broadcast CHAR to VEC_0. */
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VPBROADCAST %esi, %VMATCH
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movl %edi, %eax
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andl $(PAGE_SIZE - 1), %eax
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/* Check if we cross page boundary with one vector load.
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Otherwise it is safe to use an unaligned load. */
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cmpl $(PAGE_SIZE - VEC_SIZE), %eax
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ja L(cross_page_boundary)
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/* Check the first VEC_SIZE bytes. Search for both CHAR and the
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null bytes. */
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VMOVU (%rdi), %VMM(1)
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/* Leaves only CHARS matching esi as 0. */
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vpxorq %VMM(1), %VMATCH, %VMM(2)
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VPMINU %VMM(2), %VMM(1), %VMM(2)
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/* Each bit in K0 represents a CHAR or a null byte in VEC_1. */
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VPTESTN %VMM(2), %VMM(2), %k0
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KMOV %k0, %VRAX
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# if VEC_SIZE == 64 && defined USE_AS_STRCHRNUL
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/* If VEC_SIZE == 64 && STRCHRNUL use bsf to test condition so
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that all logic for match/null in first VEC first in 1x cache
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lines. This has a slight cost to larger sizes. */
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bsf %VRAX, %VRAX
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jz L(aligned_more)
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# else
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test %VRAX, %VRAX
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jz L(aligned_more)
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bsf %VRAX, %VRAX
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# endif
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# ifndef USE_AS_STRCHRNUL
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/* Found CHAR or the null byte. */
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cmp (%rdi, %rax, CHAR_SIZE), %CHAR_REG
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/* NB: Use a branch instead of cmovcc here. The expectation is
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that with strchr the user will branch based on input being
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null. Since this branch will be 100% predictive of the user
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branch a branch miss here should save what otherwise would
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be branch miss in the user code. Otherwise using a branch 1)
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saves code size and 2) is faster in highly predictable
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environments. */
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jne L(zero)
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# endif
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# ifdef USE_AS_WCSCHR
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/* NB: Multiply wchar_t count by 4 to get the number of bytes.
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*/
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leaq (%rdi, %rax, CHAR_SIZE), %rax
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# else
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addq %rdi, %rax
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# endif
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ret
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# ifndef USE_AS_STRCHRNUL
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L(zero):
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xorl %eax, %eax
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ret
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# endif
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.p2align 4,, 2
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L(first_vec_x3):
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subq $-(VEC_SIZE * 2), %rdi
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# if VEC_SIZE == 32
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/* Reuse L(first_vec_x3) for last VEC2 only for VEC_SIZE == 32.
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For VEC_SIZE == 64 the registers don't match. */
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L(last_vec_x2):
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# endif
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L(first_vec_x1):
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/* Use bsf here to save 1-byte keeping keeping the block in 1x
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fetch block. eax guranteed non-zero. */
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bsf %VRCX, %VRCX
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# ifndef USE_AS_STRCHRNUL
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/* Found CHAR or the null byte. */
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cmp (VEC_SIZE)(%rdi, %rcx, CHAR_SIZE), %CHAR_REG
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jne L(zero)
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# endif
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/* NB: Multiply sizeof char type (1 or 4) to get the number of
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bytes. */
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leaq (VEC_SIZE)(%rdi, %rcx, CHAR_SIZE), %rax
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ret
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.p2align 4,, 2
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L(first_vec_x4):
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subq $-(VEC_SIZE * 2), %rdi
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L(first_vec_x2):
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# ifndef USE_AS_STRCHRNUL
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/* Check to see if first match was CHAR (k0) or null (k1). */
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KMOV %k0, %VRAX
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tzcnt %VRAX, %VRAX
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KMOV %k1, %VRCX
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/* bzhil will not be 0 if first match was null. */
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bzhi %VRAX, %VRCX, %VRCX
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jne L(zero)
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# else
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/* Combine CHAR and null matches. */
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KOR %k0, %k1, %k0
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KMOV %k0, %VRAX
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bsf %VRAX, %VRAX
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# endif
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/* NB: Multiply sizeof char type (1 or 4) to get the number of
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bytes. */
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leaq (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %rax
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ret
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# ifdef USE_AS_STRCHRNUL
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/* We use this as a hook to get imm8 encoding for the jmp to
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L(page_cross_boundary). This allows the hot case of a
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match/null-term in first VEC to fit entirely in 1 cache
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line. */
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L(cross_page_boundary):
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jmp L(cross_page_boundary_real)
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# endif
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.p2align 4
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L(aligned_more):
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L(cross_page_continue):
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/* Align data to VEC_SIZE. */
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andq $-VEC_SIZE, %rdi
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/* Check the next 4 * VEC_SIZE. Only one VEC_SIZE at a time
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since data is only aligned to VEC_SIZE. Use two alternating
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methods for checking VEC to balance latency and port
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contention. */
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/* Method(1) with 8c latency:
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For VEC_SIZE == 32:
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p0 * 1.83, p1 * 0.83, p5 * 1.33
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For VEC_SIZE == 64:
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p0 * 2.50, p1 * 0.00, p5 * 1.50 */
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VMOVA (VEC_SIZE)(%rdi), %VMM(1)
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/* Leaves only CHARS matching esi as 0. */
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vpxorq %VMM(1), %VMATCH, %VMM(2)
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VPMINU %VMM(2), %VMM(1), %VMM(2)
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/* Each bit in K0 represents a CHAR or a null byte in VEC_1. */
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VPTESTN %VMM(2), %VMM(2), %k0
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KMOV %k0, %VRCX
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test %VRCX, %VRCX
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jnz L(first_vec_x1)
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/* Method(2) with 6c latency:
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For VEC_SIZE == 32:
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p0 * 1.00, p1 * 0.00, p5 * 2.00
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For VEC_SIZE == 64:
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p0 * 1.00, p1 * 0.00, p5 * 2.00 */
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VMOVA (VEC_SIZE * 2)(%rdi), %VMM(1)
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/* Each bit in K0 represents a CHAR in VEC_1. */
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VPCMPEQ %VMM(1), %VMATCH, %k0
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/* Each bit in K1 represents a CHAR in VEC_1. */
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VPTESTN %VMM(1), %VMM(1), %k1
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KORTEST %k0, %k1
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jnz L(first_vec_x2)
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/* By swapping between Method 1/2 we get more fair port
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distrubition and better throughput. */
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VMOVA (VEC_SIZE * 3)(%rdi), %VMM(1)
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/* Leaves only CHARS matching esi as 0. */
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vpxorq %VMM(1), %VMATCH, %VMM(2)
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VPMINU %VMM(2), %VMM(1), %VMM(2)
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/* Each bit in K0 represents a CHAR or a null byte in VEC_1. */
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VPTESTN %VMM(2), %VMM(2), %k0
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KMOV %k0, %VRCX
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test %VRCX, %VRCX
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jnz L(first_vec_x3)
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VMOVA (VEC_SIZE * 4)(%rdi), %VMM(1)
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/* Each bit in K0 represents a CHAR in VEC_1. */
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VPCMPEQ %VMM(1), %VMATCH, %k0
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/* Each bit in K1 represents a CHAR in VEC_1. */
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VPTESTN %VMM(1), %VMM(1), %k1
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KORTEST %k0, %k1
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jnz L(first_vec_x4)
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/* Align data to VEC_SIZE * 4 for the loop. */
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# if VEC_SIZE == 64
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/* Use rax for the loop reg as it allows to the loop to fit in
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exactly 2-cache-lines. (more efficient imm32 + gpr
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encoding). */
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leaq (VEC_SIZE)(%rdi), %rax
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/* No partial register stalls on evex512 processors. */
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xorb %al, %al
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# else
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/* For VEC_SIZE == 32 continue using rdi for loop reg so we can
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reuse more code and save space. */
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addq $VEC_SIZE, %rdi
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andq $-(VEC_SIZE * 4), %rdi
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# endif
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.p2align 4
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L(loop_4x_vec):
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/* Check 4x VEC at a time. No penalty for imm32 offset with evex
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encoding (if offset % VEC_SIZE == 0). */
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VMOVA (VEC_SIZE * 4)(%LOOP_REG), %VMM(1)
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VMOVA (VEC_SIZE * 5)(%LOOP_REG), %VMM(2)
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VMOVA (VEC_SIZE * 6)(%LOOP_REG), %VMM(3)
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VMOVA (VEC_SIZE * 7)(%LOOP_REG), %VMM(4)
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/* Collect bits where VEC_1 does NOT match esi. This is later
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use to mask of results (getting not matches allows us to
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save an instruction on combining). */
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VPCMP $4, %VMATCH, %VMM(1), %k1
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/* Two methods for loop depending on VEC_SIZE. This is because
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with zmm registers VPMINU can only run on p0 (as opposed to
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p0/p1 for ymm) so it is less prefered. */
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# if VEC_SIZE == 32
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/* For VEC_2 and VEC_3 use xor to set the CHARs matching esi to
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zero. */
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vpxorq %VMM(2), %VMATCH, %VMM(6)
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vpxorq %VMM(3), %VMATCH, %VMM(7)
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/* Find non-matches in VEC_4 while combining with non-matches
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from VEC_1. NB: Try and use masked predicate execution on
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instructions that have mask result as it has no latency
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penalty. */
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VPCMP $4, %VMATCH, %VMM(4), %k4{%k1}
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/* Combined zeros from VEC_1 / VEC_2 (search for null term). */
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VPMINU %VMM(1), %VMM(2), %VMM(2)
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/* Use min to select all zeros from either xor or end of
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string). */
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VPMINU %VMM(3), %VMM(7), %VMM(3)
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VPMINU %VMM(2), %VMM(6), %VMM(2)
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/* Combined zeros from VEC_2 / VEC_3 (search for null term). */
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VPMINU %VMM(3), %VMM(4), %VMM(4)
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/* Combined zeros from VEC_2 / VEC_4 (this has all null term and
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esi matches for VEC_2 / VEC_3). */
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VPMINU %VMM(2), %VMM(4), %VMM(4)
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# else
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/* Collect non-matches for VEC_2. */
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VPCMP $4, %VMM(2), %VMATCH, %k2
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/* Combined zeros from VEC_1 / VEC_2 (search for null term). */
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VPMINU %VMM(1), %VMM(2), %VMM(2)
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/* Find non-matches in VEC_3/VEC_4 while combining with non-
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matches from VEC_1/VEC_2 respectively. */
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VPCMP $4, %VMM(3), %VMATCH, %k3{%k1}
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VPCMP $4, %VMM(4), %VMATCH, %k4{%k2}
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/* Finish combining zeros in all VECs. */
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VPMINU %VMM(3), %VMM(4), %VMM(4)
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/* Combine in esi matches for VEC_3 (if there was a match with
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esi, the corresponding bit in %k3 is zero so the
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VPMINU_MASKZ will have a zero in the result). NB: This make
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the VPMINU 3c latency. The only way to avoid it is to
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createa a 12c dependency chain on all the `VPCMP $4, ...`
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which has higher total latency. */
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VPMINU %VMM(2), %VMM(4), %VMM(4){%k3}{z}
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# endif
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VPTEST %VMM(4), %VMM(4), %k0{%k4}
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KMOV %k0, %VRDX
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subq $-(VEC_SIZE * 4), %LOOP_REG
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/* TESTZ is inc using the proper register width depending on
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CHAR_PER_VEC. An esi match or null-term match leaves a zero-
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bit in rdx so inc won't overflow and won't be zero. */
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TESTZ (rdx)
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jz L(loop_4x_vec)
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VGPR(MASK_GPR)
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TESTZ (MASK_GPR)
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# if VEC_SIZE == 32
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/* We can reuse the return code in page_cross logic for VEC_SIZE
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== 32. */
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jnz L(last_vec_x1_vec_size32)
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# else
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jnz L(last_vec_x1_vec_size64)
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# endif
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/* COND_MASK integates the esi matches for VEC_SIZE == 64. For
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VEC_SIZE == 32 they are already integrated. */
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VPTEST %VMM(2), %VMM(2), %k0 COND_MASK(k2)
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KMOV %k0, %VRCX
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TESTZ (rcx)
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jnz L(last_vec_x2)
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VPTEST %VMM(3), %VMM(3), %k0 COND_MASK(k3)
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KMOV %k0, %VRCX
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# if CHAR_PER_VEC == 64
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TESTZ (rcx)
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jnz L(last_vec_x3)
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# else
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salq $CHAR_PER_VEC, %rdx
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TESTZ (rcx)
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orq %rcx, %rdx
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# endif
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bsfq %rdx, %rdx
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# ifndef USE_AS_STRCHRNUL
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/* Check if match was CHAR or null. */
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cmp (LAST_VEC_OFFSET)(%LOOP_REG, %rdx, CHAR_SIZE), %CHAR_REG
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jne L(zero_end)
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# endif
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/* NB: Multiply sizeof char type (1 or 4) to get the number of
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bytes. */
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leaq (LAST_VEC_OFFSET)(%LOOP_REG, %rdx, CHAR_SIZE), %rax
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ret
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# ifndef USE_AS_STRCHRNUL
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L(zero_end):
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xorl %eax, %eax
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ret
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# endif
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/* Seperate return label for last VEC1 because for VEC_SIZE ==
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32 we can reuse return code in L(page_cross) but VEC_SIZE ==
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64 has mismatched registers. */
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# if VEC_SIZE == 64
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.p2align 4,, 8
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L(last_vec_x1_vec_size64):
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bsf %VRCX, %VRCX
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# ifndef USE_AS_STRCHRNUL
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/* Check if match was null. */
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cmp (%rax, %rcx, CHAR_SIZE), %CHAR_REG
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jne L(zero_end)
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# endif
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# ifdef USE_AS_WCSCHR
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/* NB: Multiply wchar_t count by 4 to get the number of bytes.
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*/
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leaq (%rax, %rcx, CHAR_SIZE), %rax
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# else
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addq %rcx, %rax
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# endif
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ret
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/* Since we can't combine the last 2x matches for CHAR_PER_VEC
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== 64 we need return label for last VEC3. */
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# if CHAR_PER_VEC == 64
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.p2align 4,, 8
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L(last_vec_x3):
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addq $VEC_SIZE, %LOOP_REG
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# endif
|
|
|
|
/* Duplicate L(last_vec_x2) for VEC_SIZE == 64 because we can't
|
|
reuse L(first_vec_x3) due to register mismatch. */
|
|
L(last_vec_x2):
|
|
bsf %VGPR(MASK_GPR), %VGPR(MASK_GPR)
|
|
# ifndef USE_AS_STRCHRNUL
|
|
/* Check if match was null. */
|
|
cmp (VEC_SIZE * 1)(%LOOP_REG, %MASK_GPR, CHAR_SIZE), %CHAR_REG
|
|
jne L(zero_end)
|
|
# endif
|
|
/* NB: Multiply sizeof char type (1 or 4) to get the number of
|
|
bytes. */
|
|
leaq (VEC_SIZE * 1)(%LOOP_REG, %MASK_GPR, CHAR_SIZE), %rax
|
|
ret
|
|
# endif
|
|
|
|
/* Cold case for crossing page with first load. */
|
|
.p2align 4,, 10
|
|
# ifndef USE_AS_STRCHRNUL
|
|
L(cross_page_boundary):
|
|
# endif
|
|
L(cross_page_boundary_real):
|
|
/* Align rdi. */
|
|
xorq %rdi, %rax
|
|
VMOVA (PAGE_SIZE - VEC_SIZE)(%rax), %VMM(1)
|
|
/* Use high latency method of getting matches to save code size.
|
|
*/
|
|
|
|
/* K1 has 1s where VEC(1) does NOT match esi. */
|
|
VPCMP $4, %VMM(1), %VMATCH, %k1
|
|
/* K0 has ones where K1 is 1 (non-match with esi), and non-zero
|
|
(null). */
|
|
VPTEST %VMM(1), %VMM(1), %k0{%k1}
|
|
KMOV %k0, %VRAX
|
|
/* Remove the leading bits. */
|
|
# ifdef USE_AS_WCSCHR
|
|
movl %edi, %VGPR_SZ(SHIFT_REG, 32)
|
|
/* NB: Divide shift count by 4 since each bit in K1 represent 4
|
|
bytes. */
|
|
sarl $2, %VGPR_SZ(SHIFT_REG, 32)
|
|
andl $(CHAR_PER_VEC - 1), %VGPR_SZ(SHIFT_REG, 32)
|
|
|
|
/* if wcsrchr we need to reverse matches as we can't rely on
|
|
signed shift to bring in ones. There is not sarx for
|
|
gpr8/16. Also not we can't use inc here as the lower bits
|
|
represent matches out of range so we can't rely on overflow.
|
|
*/
|
|
xorl $((1 << CHAR_PER_VEC)- 1), %eax
|
|
# endif
|
|
/* Use arithmatic shift so that leading 1s are filled in. */
|
|
sarx %VGPR(SHIFT_REG), %VRAX, %VRAX
|
|
/* If eax is all ones then no matches for esi or NULL. */
|
|
|
|
# ifdef USE_AS_WCSCHR
|
|
test %VRAX, %VRAX
|
|
# else
|
|
inc %VRAX
|
|
# endif
|
|
jz L(cross_page_continue)
|
|
|
|
.p2align 4,, 10
|
|
L(last_vec_x1_vec_size32):
|
|
bsf %VRAX, %VRAX
|
|
# ifdef USE_AS_WCSCHR
|
|
/* NB: Multiply wchar_t count by 4 to get the number of bytes.
|
|
*/
|
|
leaq (%rdi, %rax, CHAR_SIZE), %rax
|
|
# else
|
|
addq %rdi, %rax
|
|
# endif
|
|
# ifndef USE_AS_STRCHRNUL
|
|
/* Check to see if match was CHAR or null. */
|
|
cmp (%rax), %CHAR_REG
|
|
jne L(zero_end_0)
|
|
# endif
|
|
ret
|
|
# ifndef USE_AS_STRCHRNUL
|
|
L(zero_end_0):
|
|
xorl %eax, %eax
|
|
ret
|
|
# endif
|
|
|
|
END (STRCHR)
|
|
#endif
|