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On some architectures, the parts of math_private.h relating to the floating-point environment are in a separate file fenv_private.h included from math_private.h. As this is purely an architecture-specific convention used by several architectures, however, all such architectures still need their own math_private.h, even if it has nothing to do beyond #include <fenv_private.h> and peculiarity of including the i386 file directly instead of having a shared file in sysdeps/x86. This patch makes the fenv_private.h name an architecture-independent convention in glibc. The include of fenv_private.h from math_private.h becomes architecture-independent (until callers are updated to include fenv_private.h directly so the include from math_private.h is no longer needed). Some architecture math_private.h headers are removed if no longer needed, or renamed to fenv_private.h if all they define belongs in that header; architecture fenv_private.h headers now do require #include_next <fenv_private.h>. The i386 fenv_private.h file moves to sysdeps/x86/fpu/ to reflect how it is actually shared with x86_64. The generic math_private.h gets a new include of <stdbool.h>, as needed for bool in some prototypes in that header (previously that was indirectly included via include/fenv.h, which now only gets included too late in math_private.h, after those prototypes). Tested for x86_64 and x86, and tested with build-many-glibcs.py that installed stripped shared libraries are unchanged by the patch. * sysdeps/aarch64/fpu/fenv_private.h: New file. Based on .... * sysdeps/aarch64/fpu/math_private.h: ... this file. All contents moved to fenv_private.h except for ... (TOINT_INTRINSICS): Kept in math_private.h. (roundtoint): Likewise. (converttoint): Likewise. * sysdeps/arm/fenv_private.h: Change multiple-include guard to [ARM_FENV_PRIVATE_H]. Include next <fenv_private.h>. * sysdeps/arm/math_private.h: Remove. * sysdeps/generic/fenv_private.h: New file. Contents moved from .... * sysdeps/generic/math_private.h: ... this file. Include <stdbool.h>. Do not include <fenv.h> or <get-rounding-mode.h>. Include <fenv_private.h>. Remove functions and macros moved to fenv_private.h. * sysdeps/i386/fpu/math_private.h: Remove. * sysdeps/mips/math_private.h: Move to .... * sysdeps/mips/fpu/fenv_private.h: ... here. Change multiple-include guard to [MIPS_FENV_PRIVATE_H]. Remove [__mips_hard_float] conditional. Include next <fenv_private.h>. * sysdeps/powerpc/fpu/fenv_private.h: Change multiple-include guard to [POWERPC_FENV_PRIVATE_H]. Include next <fenv_private.h>. * sysdeps/powerpc/fpu/math_private.h: Do not include <fenv_private.h>. * sysdeps/riscv/rvf/math_private.h: Move to .... * sysdeps/riscv/rvf/fenv_private.h: ... here. Change multiple-include guard to [RISCV_FENV_PRIVATE_H]. Include next <fenv_private.h>. * sysdeps/sparc/fpu/fenv_private.h: Change multiple-include guard to [SPARC_FENV_PRIVATE_H]. Include next <fenv_private.h>. * sysdeps/sparc/fpu/math_private.h: Remove. * sysdeps/i386/fpu/fenv_private.h: Move to .... * sysdeps/x86/fpu/fenv_private.h: ... here. Change multiple-include guard to [X86_FENV_PRIVATE_H]. Include next <fenv_private.h>. * sysdeps/x86_64/fpu/math_private.h: Do not include <sysdeps/i386/fpu/fenv_private.h>.
231 lines
7.3 KiB
C
231 lines
7.3 KiB
C
/* Private floating point rounding and exceptions handling. PowerPC version.
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Copyright (C) 2013-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef POWERPC_FENV_PRIVATE_H
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#define POWERPC_FENV_PRIVATE_H 1
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#include <fenv.h>
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#include <fenv_libc.h>
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#include <fpu_control.h>
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/* Mask for the exception enable bits. */
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#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \
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| _FPU_MASK_XM | _FPU_MASK_IM)
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/* Mask the rounding mode bits. */
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#define _FPU_MASK_RN 0xfffffffffffffffcLL
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/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */
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#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL
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/* Mask restore rounding mode and exception enabled. */
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#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL
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/* Mask FP result flags, preserve fraction rounded/inexact bits. */
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#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL
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static __always_inline void
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__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask,
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unsigned long long bits)
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{
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fenv_union_t old, new;
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old.fenv = *envp = fegetenv_register ();
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new.l = (old.l & mask) | bits;
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/* If the old env had any enabled exceptions, then mask SIGFPE in the
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MSR FE0/FE1 bits. This may allow the FPU to run faster because it
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always takes the default action and can not generate SIGFPE. */
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if ((old.l & _FPU_ALL_TRAPS) != 0)
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(void) __fe_mask_env ();
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fesetenv_register (new.fenv);
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}
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static __always_inline void
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libc_feholdexcept_ppc (fenv_t *envp)
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{
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__libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL);
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}
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static __always_inline void
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libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
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{
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__libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r);
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}
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static __always_inline void
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libc_fesetround_ppc (int r)
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{
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__fesetround_inline (r);
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}
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static __always_inline int
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libc_fetestexcept_ppc (int e)
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{
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fenv_union_t u;
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u.fenv = fegetenv_register ();
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return u.l & e;
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}
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static __always_inline void
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libc_feholdsetround_ppc (fenv_t *e, int r)
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{
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__libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r);
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}
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static __always_inline unsigned long long
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__libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
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unsigned long long new_mask)
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{
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fenv_union_t old, new;
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new.fenv = *envp;
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old.fenv = fegetenv_register ();
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/* Merge bits while masking unwanted bits from new and old env. */
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new.l = (old.l & old_mask) | (new.l & new_mask);
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/* If the old env has no enabled exceptions and the new env has any enabled
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exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
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hardware into "precise mode" and may cause the FPU to run slower on some
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hardware. */
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if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0)
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(void) __fe_nomask_env_priv ();
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/* If the old env had any enabled exceptions and the new env has no enabled
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exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
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FPU to run faster because it always takes the default action and can not
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generate SIGFPE. */
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if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0)
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(void) __fe_mask_env ();
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/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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fesetenv_register (new.fenv);
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return old.l;
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}
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static __always_inline void
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libc_fesetenv_ppc (const fenv_t *envp)
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{
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/* Replace the entire environment. */
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__libc_femergeenv_ppc (envp, 0LL, -1LL);
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}
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static __always_inline void
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libc_feresetround_ppc (fenv_t *envp)
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{
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__libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN, _FPU_MASK_FRAC_INEX_RET_CC);
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}
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static __always_inline int
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libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
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{
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return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN,
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_FPU_MASK_FRAC_INEX_RET_CC) & ex;
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}
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static __always_inline void
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libc_feupdateenv_ppc (fenv_t *e)
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{
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libc_feupdateenv_test_ppc (e, 0);
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}
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#define libc_feholdexceptf libc_feholdexcept_ppc
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#define libc_feholdexcept libc_feholdexcept_ppc
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#define libc_feholdexcept_setroundf libc_feholdexcept_setround_ppc
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#define libc_feholdexcept_setround libc_feholdexcept_setround_ppc
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#define libc_fetestexceptf libc_fetestexcept_ppc
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#define libc_fetestexcept libc_fetestexcept_ppc
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#define libc_fesetroundf libc_fesetround_ppc
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#define libc_fesetround libc_fesetround_ppc
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#define libc_fesetenvf libc_fesetenv_ppc
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#define libc_fesetenv libc_fesetenv_ppc
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#define libc_feupdateenv_testf libc_feupdateenv_test_ppc
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#define libc_feupdateenv_test libc_feupdateenv_test_ppc
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#define libc_feupdateenvf libc_feupdateenv_ppc
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#define libc_feupdateenv libc_feupdateenv_ppc
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#define libc_feholdsetroundf libc_feholdsetround_ppc
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#define libc_feholdsetround libc_feholdsetround_ppc
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#define libc_feresetroundf libc_feresetround_ppc
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#define libc_feresetround libc_feresetround_ppc
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/* We have support for rounding mode context. */
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#define HAVE_RM_CTX 1
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static __always_inline void
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libc_feholdsetround_ppc_ctx (struct rm_ctx *ctx, int r)
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{
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fenv_union_t old, new;
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old.fenv = fegetenv_register ();
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new.l = (old.l & _FPU_MASK_TRAPS_RN) | r;
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ctx->env = old.fenv;
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if (__glibc_unlikely (new.l != old.l))
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{
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if ((old.l & _FPU_ALL_TRAPS) != 0)
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(void) __fe_mask_env ();
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fesetenv_register (new.fenv);
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ctx->updated_status = true;
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}
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else
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ctx->updated_status = false;
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}
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static __always_inline void
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libc_fesetenv_ppc_ctx (struct rm_ctx *ctx)
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{
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libc_fesetenv_ppc (&ctx->env);
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}
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static __always_inline void
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libc_feupdateenv_ppc_ctx (struct rm_ctx *ctx)
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{
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if (__glibc_unlikely (ctx->updated_status))
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libc_feresetround_ppc (&ctx->env);
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}
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static __always_inline void
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libc_feresetround_ppc_ctx (struct rm_ctx *ctx)
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{
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if (__glibc_unlikely (ctx->updated_status))
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libc_feresetround_ppc (&ctx->env);
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}
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#define libc_fesetenv_ctx libc_fesetenv_ppc_ctx
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#define libc_fesetenvf_ctx libc_fesetenv_ppc_ctx
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#define libc_fesetenvl_ctx libc_fesetenv_ppc_ctx
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#define libc_feholdsetround_ctx libc_feholdsetround_ppc_ctx
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#define libc_feholdsetroundf_ctx libc_feholdsetround_ppc_ctx
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#define libc_feholdsetroundl_ctx libc_feholdsetround_ppc_ctx
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#define libc_feresetround_ctx libc_feresetround_ppc_ctx
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#define libc_feresetroundf_ctx libc_feresetround_ppc_ctx
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#define libc_feresetroundl_ctx libc_feresetround_ppc_ctx
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#define libc_feupdateenv_ctx libc_feupdateenv_ppc_ctx
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#define libc_feupdateenvf_ctx libc_feupdateenv_ppc_ctx
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#define libc_feupdateenvl_ctx libc_feupdateenv_ppc_ctx
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#include_next <fenv_private.h>
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#endif
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