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https://sourceware.org/git/glibc.git
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cb3a749a22
Fixes and partially reverts commit 59803e81f9
("x86: Optimizing memcpy for AMD Zen architecture.").
430 lines
15 KiB
C
430 lines
15 KiB
C
/* x86 cache info.
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Copyright (C) 2020 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <assert.h>
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#include <unistd.h>
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/* Data cache size for use in memory and string routines, typically
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L1 size, rounded to multiple of 256 bytes. */
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long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
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long int __x86_data_cache_size attribute_hidden = 32 * 1024;
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/* Similar to __x86_data_cache_size_half, but not rounded. */
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long int __x86_raw_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
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/* Similar to __x86_data_cache_size, but not rounded. */
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long int __x86_raw_data_cache_size attribute_hidden = 32 * 1024;
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/* Shared cache size for use in memory and string routines, typically
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L2 or L3 size, rounded to multiple of 256 bytes. */
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long int __x86_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
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long int __x86_shared_cache_size attribute_hidden = 1024 * 1024;
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/* Similar to __x86_shared_cache_size_half, but not rounded. */
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long int __x86_raw_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
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/* Similar to __x86_shared_cache_size, but not rounded. */
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long int __x86_raw_shared_cache_size attribute_hidden = 1024 * 1024;
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/* Threshold to use non temporal store. */
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long int __x86_shared_non_temporal_threshold attribute_hidden;
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/* Threshold to use Enhanced REP MOVSB. */
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long int __x86_rep_movsb_threshold attribute_hidden = 2048;
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/* Threshold to use Enhanced REP STOSB. */
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long int __x86_rep_stosb_threshold attribute_hidden = 2048;
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static void
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get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr,
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long int core)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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/* Number of logical processors sharing L2 cache. */
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int threads_l2;
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/* Number of logical processors sharing L3 cache. */
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int threads_l3;
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const struct cpu_features *cpu_features = __get_cpu_features ();
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int max_cpuid = cpu_features->basic.max_cpuid;
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unsigned int family = cpu_features->basic.family;
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unsigned int model = cpu_features->basic.model;
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long int shared = *shared_ptr;
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unsigned int threads = *threads_ptr;
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bool inclusive_cache = true;
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bool support_count_mask = true;
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/* Try L3 first. */
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unsigned int level = 3;
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if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6)
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support_count_mask = false;
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if (shared <= 0)
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{
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/* Try L2 otherwise. */
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level = 2;
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shared = core;
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threads_l2 = 0;
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threads_l3 = -1;
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}
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else
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{
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threads_l2 = 0;
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threads_l3 = 0;
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}
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/* A value of 0 for the HTT bit indicates there is only a single
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logical processor. */
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if (HAS_CPU_FEATURE (HTT))
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{
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/* Figure out the number of logical threads that share the
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highest cache level. */
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if (max_cpuid >= 4)
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{
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int i = 0;
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/* Query until cache level 2 and 3 are enumerated. */
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int check = 0x1 | (threads_l3 == 0) << 1;
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do
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{
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__cpuid_count (4, i++, eax, ebx, ecx, edx);
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/* There seems to be a bug in at least some Pentium Ds
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which sometimes fail to iterate all cache parameters.
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Do not loop indefinitely here, stop in this case and
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assume there is no such information. */
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if (cpu_features->basic.kind == arch_kind_intel
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&& (eax & 0x1f) == 0 )
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goto intel_bug_no_cache_info;
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switch ((eax >> 5) & 0x7)
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{
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default:
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break;
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case 2:
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if ((check & 0x1))
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{
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/* Get maximum number of logical processors
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sharing L2 cache. */
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threads_l2 = (eax >> 14) & 0x3ff;
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check &= ~0x1;
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}
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break;
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case 3:
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if ((check & (0x1 << 1)))
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{
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/* Get maximum number of logical processors
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sharing L3 cache. */
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threads_l3 = (eax >> 14) & 0x3ff;
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/* Check if L2 and L3 caches are inclusive. */
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inclusive_cache = (edx & 0x2) != 0;
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check &= ~(0x1 << 1);
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}
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break;
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}
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}
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while (check);
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/* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum
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numbers of addressable IDs for logical processors sharing
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the cache, instead of the maximum number of threads
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sharing the cache. */
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if (max_cpuid >= 11 && support_count_mask)
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{
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/* Find the number of logical processors shipped in
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one core and apply count mask. */
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i = 0;
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/* Count SMT only if there is L3 cache. Always count
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core if there is no L3 cache. */
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int count = ((threads_l2 > 0 && level == 3)
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| ((threads_l3 > 0
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|| (threads_l2 > 0 && level == 2)) << 1));
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while (count)
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{
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__cpuid_count (11, i++, eax, ebx, ecx, edx);
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int shipped = ebx & 0xff;
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int type = ecx & 0xff00;
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if (shipped == 0 || type == 0)
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break;
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else if (type == 0x100)
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{
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/* Count SMT. */
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if ((count & 0x1))
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{
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int count_mask;
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/* Compute count mask. */
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asm ("bsr %1, %0"
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: "=r" (count_mask) : "g" (threads_l2));
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count_mask = ~(-1 << (count_mask + 1));
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threads_l2 = (shipped - 1) & count_mask;
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count &= ~0x1;
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}
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}
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else if (type == 0x200)
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{
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/* Count core. */
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if ((count & (0x1 << 1)))
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{
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int count_mask;
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int threads_core
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= (level == 2 ? threads_l2 : threads_l3);
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/* Compute count mask. */
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asm ("bsr %1, %0"
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: "=r" (count_mask) : "g" (threads_core));
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count_mask = ~(-1 << (count_mask + 1));
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threads_core = (shipped - 1) & count_mask;
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if (level == 2)
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threads_l2 = threads_core;
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else
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threads_l3 = threads_core;
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count &= ~(0x1 << 1);
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}
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}
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}
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}
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if (threads_l2 > 0)
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threads_l2 += 1;
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if (threads_l3 > 0)
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threads_l3 += 1;
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if (level == 2)
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{
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if (threads_l2)
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{
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threads = threads_l2;
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if (cpu_features->basic.kind == arch_kind_intel
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&& threads > 2
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&& family == 6)
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switch (model)
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{
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case 0x37:
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case 0x4a:
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case 0x4d:
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case 0x5a:
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case 0x5d:
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/* Silvermont has L2 cache shared by 2 cores. */
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threads = 2;
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break;
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default:
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break;
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}
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}
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}
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else if (threads_l3)
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threads = threads_l3;
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}
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else
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{
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intel_bug_no_cache_info:
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/* Assume that all logical threads share the highest cache
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level. */
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threads
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= ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx
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>> 16) & 0xff);
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}
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/* Cap usage of highest cache level to the number of supported
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threads. */
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if (shared > 0 && threads > 0)
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shared /= threads;
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}
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/* Account for non-inclusive L2 and L3 caches. */
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if (!inclusive_cache)
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{
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if (threads_l2 > 0)
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core /= threads_l2;
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shared += core;
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}
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*shared_ptr = shared;
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*threads_ptr = threads;
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}
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static void
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init_cacheinfo (void)
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{
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/* Find out what brand of processor. */
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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int max_cpuid_ex;
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long int data = -1;
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long int shared = -1;
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long int core;
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unsigned int threads = 0;
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const struct cpu_features *cpu_features = __get_cpu_features ();
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/* NB: In libc.so, cpu_features is defined in ld.so and is initialized
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by DL_PLATFORM_INIT or IFUNC relocation before init_cacheinfo is
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called by IFUNC relocation. In libc.a, init_cacheinfo is called
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from init_cpu_features by ARCH_INIT_CPU_FEATURES. */
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assert (cpu_features->basic.kind != arch_kind_unknown);
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if (cpu_features->basic.kind == arch_kind_intel)
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{
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data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
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core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
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get_common_cache_info (&shared, &threads, core);
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}
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else if (cpu_features->basic.kind == arch_kind_zhaoxin)
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{
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data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE);
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core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
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get_common_cache_info (&shared, &threads, core);
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}
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else if (cpu_features->basic.kind == arch_kind_amd)
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{
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data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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/* Get maximum extended function. */
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__cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx);
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if (shared <= 0)
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/* No shared L3 cache. All we have is the L2 cache. */
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shared = core;
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else
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{
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/* Figure out the number of logical threads that share L3. */
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if (max_cpuid_ex >= 0x80000008)
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{
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/* Get width of APIC ID. */
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__cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx);
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threads = 1 << ((ecx >> 12) & 0x0f);
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}
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if (threads == 0 || cpu_features->basic.family >= 0x17)
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{
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/* If APIC ID width is not available, use logical
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processor count. */
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__cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx);
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if ((edx & (1 << 28)) != 0)
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threads = (ebx >> 16) & 0xff;
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}
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/* Cap usage of highest cache level to the number of
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supported threads. */
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if (threads > 0)
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shared /= threads;
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/* Get shared cache per ccx for Zen architectures. */
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if (cpu_features->basic.family >= 0x17)
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{
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unsigned int eax;
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/* Get number of threads share the L3 cache in CCX. */
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__cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
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unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
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shared *= threads_per_ccx;
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}
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else
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{
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/* Account for exclusive L2 and L3 caches. */
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shared += core;
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}
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}
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}
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/* Prefer cache size configure via tuning. */
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if (cpu_features->data_cache_size != 0)
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data = cpu_features->data_cache_size;
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if (data > 0)
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{
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__x86_raw_data_cache_size_half = data / 2;
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__x86_raw_data_cache_size = data;
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/* Round data cache size to multiple of 256 bytes. */
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data = data & ~255L;
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__x86_data_cache_size_half = data / 2;
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__x86_data_cache_size = data;
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}
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/* Prefer cache size configure via tuning. */
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if (cpu_features->shared_cache_size != 0)
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shared = cpu_features->shared_cache_size;
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if (shared > 0)
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{
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__x86_raw_shared_cache_size_half = shared / 2;
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__x86_raw_shared_cache_size = shared;
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/* Round shared cache size to multiple of 256 bytes. */
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shared = shared & ~255L;
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__x86_shared_cache_size_half = shared / 2;
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__x86_shared_cache_size = shared;
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}
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/* The default setting for the non_temporal threshold is 3/4 of one
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thread's share of the chip's cache. For most Intel and AMD processors
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with an initial release date between 2017 and 2020, a thread's typical
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share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4
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threshold leaves 125 KBytes to 500 KBytes of the thread's data
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in cache after a maximum temporal copy, which will maintain
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in cache a reasonable portion of the thread's stack and other
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active data. If the threshold is set higher than one thread's
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share of the cache, it has a substantial risk of negatively
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impacting the performance of other threads running on the chip. */
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__x86_shared_non_temporal_threshold
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= (cpu_features->non_temporal_threshold != 0
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? cpu_features->non_temporal_threshold
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: __x86_shared_cache_size * 3 / 4);
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/* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */
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unsigned int minimum_rep_movsb_threshold;
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/* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */
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unsigned int rep_movsb_threshold;
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F)
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&& !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512))
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{
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rep_movsb_threshold = 2048 * (64 / 16);
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minimum_rep_movsb_threshold = 64 * 8;
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}
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else if (CPU_FEATURE_PREFERRED_P (cpu_features,
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AVX_Fast_Unaligned_Load))
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{
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rep_movsb_threshold = 2048 * (32 / 16);
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minimum_rep_movsb_threshold = 32 * 8;
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}
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else
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{
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rep_movsb_threshold = 2048 * (16 / 16);
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minimum_rep_movsb_threshold = 16 * 8;
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}
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if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold)
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__x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold;
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else
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__x86_rep_movsb_threshold = rep_movsb_threshold;
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# if HAVE_TUNABLES
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__x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold;
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# endif
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}
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